Etching method

Abstract

The invention discloses an etching method, and the method comprises the steps: carrying out the machining of a first semi-finished product which is used for manufacturing a trench VDMOS device, wherein the first semi-finished product comprises a first substrate and an epitaxial layer formed on the first substrate, and the epitaxial layer is at least provided with a first body region; at least forming a first source region and a second source region adjacent to the first source region in the body region; forming a first trench in the first source region through downward etching, and forming a second trench in the second source region through downward etching. The method also comprises the steps: growing a gate-oxide layer and a first polycrystalline silicon layer on the upper surface of the first semi-finished product; thinning the first polycrystalline silicon layer, so as to forming a residual polycrystalline silicon layer with a preset thickness; and carrying out the photoetching and etching of the residual polycrystalline silicon layer so as to at least form a first polycrystalline silicon grid electrode in the first trench and a second polycrystalline silicon grid electrode in the second trench.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to an etching method. Background technique [0002] VDMOS, that is, vertical double diffused metal-oxide semiconductor field effect transistor, VDMOS has the advantages of both bipolar transistors and ordinary MOS devices. Whether it is a switch application or a linear application, VDMOS is an ideal power device. VDMOS is mainly used in motor regulation. speed, inverter, uninterruptible power supply, electronic switch, hi-fi, automotive electrical appliances and electronic ballast, etc. Trench-type VDMOS adopts the trench etching technology invented in the preparation process of memory storage capacitors, so that the conductive trench changes from horizontal to vertical. Compared with the ordinary VDMOS structure, the resistance of the JFET neck area is eliminated. Therefore, the cell size is greatly increased. density, increasing the current handling capability of power ...

AI Technical Summary

Problems solved by technology

[0004] Since the trench VDMOS is designed differently for different devices, the distance between the trenches is large or small. When the distance between the trenches is small, the polysilicon gate protrusion is high, resulting in the dielectric layer deposition in the subsequent process. The layers are connected or hollow, such as figure 1 and as figure 2 As shown, therefore, the prior art solution has the technical problem that the photolithography and etching of the contact hole are difficult when the dielectric layer is connected, and there is even a technical problem that the contact hole cannot be formed when the dielectric layer is hollow.

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