Method of performing full linear error-free protection transmission on multimedia data
A multimedia data and full-line technology, applied in digital transmission systems, transmission systems, error prevention, etc., can solve problems such as image quality degradation, high hardware costs, and cliff effects
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Embodiment 1
[0076] A schematic diagram of the processing flow of the encoding and transmitting part and the receiving and decoding part in the method for performing full-linear non-error-correction-protected transmission of picture multimedia data in the embodiment of the present invention is as follows figure 1 As shown, among them, figure 1 The encoded transmission part shown in A includes the following processing steps:
[0077] Step 1, separate each frame of the image multimedia data to be transmitted independently to obtain M frames, and take a 2 in one frame N ×2 N module, the M and N are set integers. The above multimedia data may be video data or picture data.
[0078] Step 2, will 2 N ×2 N After subtracting 128 from each pixel in the module, a decorrelation transformation is performed to obtain a decorrelation transformation coefficient matrix.
[0079] Step 3, will 2 N ×2 N The decorrelation transformation coefficient matrix of the module is obtained by data rearrangemen...
Embodiment 2
[0123] FPGA+DSP implementation method: Due to the need for real-time video encoding and decoding (especially the receiving and decoding part), the FPGA+DSP implementation method becomes very necessary. The implementation of this scheme is divided into two parts: encoding, transmitting and receiving and decoding, which are respectively implemented on two Xilinx KC705FPGA development boards.
[0124] In this implementation scheme, the module size is 8×8 (that is, N=3), and M=256 at the same time. The communication system is realized by OFDM system, the de-correlation transformation is DCT transformation, the data rearrangement uses zigzage algorithm, and the whitening transformation adopts Wash-Hadamard transformation. The specific implementation plan is as follows:
[0125] 1.1) The schematic diagram of the hardware system structure of the encoding and transmitting part of the embodiment of the present invention is as follows: Figure 5 As shown, the hardware part of the enco...
Embodiment 3
[0152] 2): Implementation of software radio:
[0153] In this implementation scheme, the module size is 8×8 (that is, N=3), and M=256 at the same time. The communication system is realized by OFDM system, the de-correlation transformation is DCT transformation, the data rearrangement uses zigzage algorithm, and the whitening transformation adopts Wash-Hadamard transformation. The specific implementation plan is as follows:
[0154] Source channel coding and decoding is completed by software on the PC, and high-speed digital signal processing and RF transmission and reception are completed on the USRP N210 motherboard. The software radio architecture structure diagram of the embodiment of the present invention is as follows Figure 9 As shown, the hardware part: it is composed of PC, software radio development board, and RF radio frequency chip.
[0155] 2.1) PC: through Matlab software architecture AnalogCast source codec end, linear OFDM channel codec end.
[0156] 2.3) S...
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