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Lead wire framework based on DIP multiple substrates and method of using lead wire framework to manufacture packaging part

A lead frame and package technology, which is applied in the field of lead frames based on DIP multi-base islands, can solve the problems of multiple encapsulation resins, small number of chips, single function, etc., achieve packaging cost savings, increase packaging yield, and reduce consumption Effect

Active Publication Date: 2015-09-23
TIANSHUI HUATIAN TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] At present, integrated circuit packaging, in the design of the base island carrying the chip, mostly adopts the design of a single or two base islands. The number of chips packaged by this design is small (1 or 2), and the product cost for the packaging factory is relatively low. Higher (1 chip or 2 chips require longer bonding wires, more encapsulating resin), and realize single function (analog or mixed signal) at the same time

Method used

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  • Lead wire framework based on DIP multiple substrates and method of using lead wire framework to manufacture packaging part
  • Lead wire framework based on DIP multiple substrates and method of using lead wire framework to manufacture packaging part
  • Lead wire framework based on DIP multiple substrates and method of using lead wire framework to manufacture packaging part

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0080] Using an 8-12 inch wafer thickness thinning machine, the wafer is thinned under the condition of the spindle speed of 2400rpm. The thickness of the chip obtained by thinning is 380μm, and the surface roughness of the chip is Ra0.10mm; the thinning process is the same as that of conventional QFN thinning , coarse grinding + fine grinding and polishing; on the 8-12 inch wafer dicing machine, the chip is diced by using the general dicing process of DIP package; Pick up the first IC chip from the wafer, place it on the adhesive of the first base island, complete the bonding of the first IC chip on the first frame unit, and then bond it on the fourth base island of the second frame unit For the first IC chip, the bonding of the first IC chip on each frame unit of the entire frame is carried out sequentially. After the first IC chip of the entire frame is bonded, the bonding of the first IC chip of the second frame is carried out until the entire frame The first IC chip of th...

Embodiment 2

[0082] Wafer thinning, dicing and core loading are carried out using the method of Example 1. The spindle speed during wafer thinning is 3000rpm, the lifting height of the core on the suction nozzle is 6500step, the lifting height of the thimble is 160mm, and the thimble is rising. The delay time is 10ms, the dispensing height is 2000step, the thickness of the adhesive is 38μm, the pick-up force of the adhesive is 1N, and the adhesive force of the adhesive is 1N; Baking nitrogen flow rate > 0.8m 2 / h; pressure welding according to the method of Example 1: using a suitable copper wire process, the substrate heating temperature is 220 ° C, the ignition flow rate is adjusted to 3100 μA, the ignition discharge time is adjusted to 710 μs, and the copper ball head is melted to obtain a smooth surface And flawless gold ball FAB, the time of 13ms ultrasonic wave and pressure is added to the wiring chopper, the ultrasonic frequency is 130KHZ, the output mode is current, the power is ab...

Embodiment 3

[0084] Wafer thinning, dicing and core loading are carried out using the method of Example 1. The spindle speed during wafer thinning is 2700rpm, the lifting height of the core on the suction nozzle is 5250step, the lifting height of the thimble is 130mm, and the thimble rises The delay time is 7.5ms, the dispensing height is 1700step, the thickness of the adhesive is 23μm, the pick-up force of the adhesive is 0.75N, and the adhesive force of the adhesive is 0.75N; after the core is completed, it is baked for 3 hours using the anti-separation layer baking process , curing and baking nitrogen flow > 0.8m 2 / h; pressure welding is carried out according to the method of Example 1: adopt a suitable copper wire process, the substrate heating temperature is 210°C, adjust the ignition flow rate to 2850μA, adjust the ignition discharge time to 670μs, and melt the gold ball head to obtain a smooth surface And flawless gold ball FAB, the time of 7ms ultrasonic wave and pressure is added...

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Abstract

Provided is a lead wire framework based on DIP multiple substrates and a method of using the lead wire framework to manufacture a packaging part. The lead wire framework comprises a framework body with a plurality of rows of first framework unit sets and a plurality of rows of second framework unit sets, and the two kinds of framework unit sets are arranged at intervals. A framework unit is provided with three substrates, wherein two substrates are in connection with four inner pins of the framework unit through a dam bar, and are located between a third substrate and the dam bar; the third substrate is in connection with the frame of the framework body through a tie bar; the inner pin in the framework unit towards an adjacent framework unit and the inner pin of the adjacent framework unit towards the framework unit are interlaced. A wafer is thinned and sawed, and a chip is adhered to the lead wire framework according to requirements to obtain a packing part through processes including pressure welding, post curing, plastic package, etc. The lead wire framework is conductive to increasing product function integration, and improving product packaging yield, quality and reliability; in addition, the lead wire framework can be extended to multi-row matrix type packaging, and is not limited to a DIP packaging form.

Description

technical field [0001] The invention belongs to the technical field of semiconductor manufacturing, and relates to a lead frame, in particular to a lead frame based on DIP multi-base islands; the invention also relates to a method for manufacturing a package with the lead frame. Background technique [0002] For a long time, most of the packaging and manufacturing of DIP series products are single-carrier or double-carrier two-row lead frame mode. , Rebar trimming and forming mold technology, recognition accuracy of core / press welding equipment and working window range, the traditional single / double base island two-row frame mode not only has low production efficiency, but also causes great waste of factory capacity and manpower. . Moreover, the consistency of product dimensions is poor, and the packaging yield is low, resulting in high production costs and low efficiency. [0003] After years of exploration and development, according to market changes in low-cost, high-pa...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/495H01L21/60
CPCH01L2924/181H01L2224/32145H01L2224/32245H01L2224/45144H01L2224/45147H01L2224/48091H01L2224/48137H01L2224/48145H01L2224/48247H01L2224/48465H01L2224/73265H01L2224/97H01L2924/00012H01L2924/00014H01L2924/00
Inventor 牛社强孙亚丽
Owner TIANSHUI HUATIAN TECH
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