First in first out storer circuit structure based on random access memory (RAM)

A circuit structure, first-in-first-out technology, applied in the field of rapid implementation of parallel scheduling, can solve the problems of increased design structure links, increased processing links, increased delays, etc., to reduce design complexity, simplify circuit structure, and speed up the processing process. Effect

Active Publication Date: 2015-07-15
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
View PDF3 Cites 12 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This makes the whole design process complicated, increases the design structure links, complicates the timing and functions, and increases the delay in some cases, thus complicating the circuit...

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • First in first out storer circuit structure based on random access memory (RAM)

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0016] Referring to the accompanying drawings, a brief description will be given below of the implementation of the content of the present invention.

[0017] Taking the currently designed high-speed network protocol chip as an example, in the design, after the multi-channel message data is received in parallel through the interface module, it enters the protocol processing module at the same time, and the multi-channel input and single-output FIFO is used for receiving and sorting, and then sequentially output to the Protocol processing module. Here, taking a FIFO with 2 channels of input and 1 channel of output as an example, the circuit structure and operation mode of this type of FIFO design are explained: when two channels of messages arrive at the FIFO at the same time and the FIFO read data signal is enabled at the same time, the FIFO simultaneously receives For the two-way message data, first obtain the writable address information in the current RAM according to the w...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention provides a first in first out storer circuit structure based on a random access memory (RAM) and relates to the field of chip design. A multi-input single-output FIFO structure body is established, a multi-access interface RAM storage body is established through at least three ordinary single-access interface RAM storage bodies, a configurable ranking mode is set, an independent read-write FIFO pointer is set, an FIFO upper overflowing error mark is achieved through a marked vector mark bit corresponding to an address in writing, and an FIFO lower overflowing error mark is output through an unmarked vector mark bit corresponding to the address in reading. By means of a novel FIFO structure, multi-channel message parallel writing FIFO can be directly achieved. Furthermore, automatic ranking can be achieved according to a set mode, serial can be output through FIFO, and a parallel storage function and a serial scheduling function can be automatically achieved.

Description

technical field [0001] The invention relates to the field of chip design, in particular to a fast implementation method for parallel scheduling of data paths in the circuit implementation process of network control protocol chips in a multi-node network. Background technique [0002] With the continuous development of the server application field, the application requirements of high-end servers have entered an important stage. The realization of complex architecture supports high-end server systems to achieve high performance indicators, high security, high availability, and high reliability. This requires a network control chip to control the multi-processor system, so that the internal message transmission of the system can be efficient, reliable, safe and stable. For the design of this type of control chip, efficient scheduling of multi-channel high-speed packets is very necessary. In this case, the scheduling of multi-channel high-speed packets generally requires an a...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G06F5/06
Inventor 赵元刘强
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap