Method for manufacturing embedded source/drain MOS transistors

Abstract

The invention provides a method for manufacturing embedded source / drain MOS transistors. The method comprises the steps that gate structures are formed on a PMOS transistor area and an NMOS transistor area formed on a semiconductor substrate respectively, and an STI is arranged between the PMOS transistor area and the NMOS transistor area; channels adjacent to the two sides of each gate structure are synchronously formed on the PMOS transistor area and the NMOS transistor area; after first strained silicon grows in the channels of the PMOS transistor area and the NMOS transistor area, first embedded source / drain electrodes are synchronously formed; a barrier layer is disposed on the PMOS transistor area; after acid gas is used for etching the first embedded source / drain electrode in the NMOS transistor area so that second strained silicon can grow in the channels in the totally exposed PMOS pipe area, second embedded source / drain electrodes are formed; the barrier layer disposed on the PMOS transistor area is removed. According to the method, the existing technological steps of manufacturing the embedded source / drain MOS transistors can be optimized, and manufacturing cost can also be lowered.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and in particular relates to a manufacturing method of an embedded source / drain MOS transistor. Background technique [0002] CMOS devices have continued to shrink in size over the past few decades. In early semiconductor circuit technology, the channel length in CMOS devices was on the order of several microns. By the end of the 1990s, the size of CMOS devices continued to shrink, which greatly improved the performance of semiconductor circuits. In today's semiconductor circuit technology, this parameter has been reduced by dozens of times or even more than one hundred times. [0003] However, the reduction in the size of CMOS devices also brings some negative issues. For example, a smaller channel width increases the channel equivalent resistance. With the in-depth research on the piezoresistance effect of silicon materials, the industry has gradually ...

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Problems solved by technology

[0018] It can be seen that the existing manufacturing methods of CMOS devices with e-SiGe source / drain and e-SiC source / drain need to etch the silicon substrate at least twice to form the e-SiGe source respectively. / drain grooves and grooves for e-SiC source / drain electrodes, and each time in order to form one of the grooves, multiple steps are required, especially in the removal of photoresist and barrier layer. process steps, the lithography used is extremely expensive

Therefore, the above-mentioned manufacturing method not only has cumbersome steps, but also has extremely high manufacturing costs.

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