An anti-staggered layer heterojunction resonant tunneling field effect transistor and its preparation method

Abstract

The invention discloses an anti-staggered-layer heterojunction resonance tunneling field-effect transistor (TFET) and a preparation method thereof. The TFET comprises a tunneling source region, a channel region, a drain region and a control grid located above the channel region, wherein an electronic band structure of a heterogeneous tunneling junction of the tunneling source region and an electronic band structure of a heterogeneous tunneling junction of the channel region are respectively an anti-staggered-layer heterojunction. If the TFET is an N type device, the bottom of a conduction band of the tunneling source region is located below the valence band top of the channel region at the juncture surface of the heterogeneous tunneling junction of the tunneling source region and the heterogeneous tunneling junction of the channel region; if the TFET is a P type device, the valence band top of the tunneling source region is located above the bottom of a conduction band of the channel region. Thus, on-state currents of the TFET can be remarkably increased; meanwhile, off-state currents of the device are effectively suppressed, and a steep subthreshold slope is maintained. According to the preparation method of the TFET, a low-power dissipation integrated circuit formed by TFETs is prepared by effectively using a standard process, production cost is greatly reduced, and the process is simple.

Description

technical field [0001] The invention belongs to the field of CMOS ultra large scale integrated circuit (ULSI) field effect transistor logic devices, and specifically relates to an anti-staggered layer type heterojunction resonant tunneling field effect transistor and a preparation method thereof. Background technique [0002] Since the birth of integrated circuits, microelectronics integration technology has been developing continuously in accordance with "Moore's Law", and the size of semiconductor devices has been continuously reduced. As semiconductor devices enter the deep submicron range, existing MOSFET devices are limited by the conduction mechanism of self-diffusion drift, and the subthreshold slope is limited by the thermoelectric potential kT / q, which cannot be reduced synchronously with the reduction of device size. As a result, the reduction of leakage current of MOSFET devices cannot meet the requirements of device size reduction, the energy consumption of the e...

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Problems solved by technology

[0003] However, due to the low efficiency of semiconductor band-band tunneling, the on-state current of TFET is lower than that of existing MOSFETs, which cannot meet the requirements of system integration applications.

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