Method for avoiding negative bias temperature instability of device

Abstract

The invention provides a method for avoiding negative bias temperature instability of a device. The method includes the steps that a wet method deposition process is utilized to replace a dry method deposition process to deposit a grid electrode oxidation layer; after the grid electrode oxidation layer is deposited, oxidizing gas is fed into an oxidation process cavity in which the device to be processed is placed through a high-temperature heat oxidation process so that a grid electrode isolation film can grow. When the grid electrode isolation film grows through the high-temperature heat oxidation process, dichlorosilane is mixed into the oxidizing gas, and then the high-temperature heat oxidation process of the grid electrode isolation film can be finished.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, and more specifically, the invention relates to a method for improving the temperature instability of negative bias voltage of devices by improving furnace tube technology. Background technique [0002] When the PMOS device is working, when the gate is under negative bias, after a certain period of time, the absolute value of the threshold voltage of the device will continue to increase, and the drain current and transconductance will continue to decrease. This effect will increase with the bias voltage increase more significantly. [0003] In the existing manufacturing process, the gate oxide layer (Gate 1 oxide) adopts a Wet deposition process. During the process, H is introduced to form H+, which drifts toward the gate under the action of the gate electric field. Some It will be trapped by defects in the oxide layer to form trap charges in the positive oxide layer. This part of the ...

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Problems solved by technology

[0003] In the existing manufacturing process, the gate oxide layer (Gate 1 oxide) adopts a Wet deposition process. During the process, H is introduced to form H+, which drifts toward the gate under the action of the gate electric field. Some It will be trapped by defects in the oxide layer to form trap charges in the positive oxide layer. This part of the charge will cause a shift in the threshold voltage and weaken the gate control ability. Under the same gate voltage and drain voltage, the degree of inversion layer is reduced, and the saturation current decrease, the driving energy of the device decreases; another part of H+ will continue to interact with the Si-H bond at the interface to make Si-H decompose and form H2, leaving the interface trap that is the dangling bond of trivalent silicon, and the generation of interface trap will lead to The increase of the surface scattering rate, thus affecting the carrier mobility, transconductance, etc.

As a result, the negative bias temperature instability NBTI (Negative bias temperature instability) of the device is affected

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