Transistor gate array with different lengths and fabrication method thereof

A manufacturing method and transistor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problem of limited time-consuming deviation, achieve the effect of reducing deviation, easy to implement, and not involving complicated calculations

Active Publication Date: 2016-08-03
SEMICON MFG INT (SHANGHAI) CORP
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, the above-mentioned optical proximity correction method involves a large amount of calculations, and different pattern layouts require different calculation processes, which is time-consuming and reduces the amount of deviation limited.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Transistor gate array with different lengths and fabrication method thereof
  • Transistor gate array with different lengths and fabrication method thereof
  • Transistor gate array with different lengths and fabrication method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0058] In the first embodiment, the fabrication method of the present invention is introduced by taking the target array, that is, the case where the lengths of the gates in the grid array to be formed are not equal, as an example. Specifically, such as figure 1 The target gate array with 4 gates is shown, the lengths of gates 1, 2, 3, 4 are d 1 、d 2 、d 3 、d 4 , which ranges, for example, from 0.03 microns to 3 microns. Among them, in the vertical gate length direction, that is, in the X direction, the lower end of the gate 1 in the array is the longest, and the upper end of the gate 2 is the longest, and the overlapping length of the two gates 1 and 2 in the length direction is s; The widths of poles 1, 2, 3, and 4 can be equal or unequal, and the distance between gate 1 and gate 2 is w 1 , the distance between gate 2 and gate 3 is w 2 , the distance between gate 3 and gate 4 is w 3 , where w 1 、w 2 、w 3 Can be equal or unequal. In one embodiment, the widths of the...

Embodiment 2

[0076] The second embodiment still introduces the manufacturing method of the present invention by taking the case that the lengths of the gates in the target array are not equal as an example. The difference from Embodiment 1 is that the target array has the longest gate, and the two ends of other gates in the target array do not exceed the two ends of the longest gate along the vertical gate length direction. Specifically, such as Figure 7 The target gate array with 4 gates is shown, where the length of gate 1 d 1 The longest, the two ends of the other gates 2, 3, 4 are along the vertical gate length direction, that is, the X direction, and do not exceed the two ends of the longest gate 1.

[0077] When using the first mask A' to expose the first photoresist 103 (positive photoresist) on the polysilicon 102 in step S12, as Figure 8 As shown, each light-shielding pattern ( Figure 8 The shaded area in ) is the length d of the longest gate 1 in the target array 1 . In o...

Embodiment 3

[0086] The transistor gate arrays with different lengths provided in the third embodiment and the manufacturing method thereof are substantially the same as those in the second embodiment. The difference is that the transistor gate target array has multiple sub-arrays, for example, as Figure 12 As shown, for sub-arrays 1', 2', 3', and 4', the target gate lengths of each sub-array are equal, and the target gate lengths of different sub-arrays are different, and each gate of sub-array 1' is the longest gate , the two ends of the gates of other sub-arrays in the target array do not exceed the two ends of the longest gate along the vertical gate length direction.

[0087] It can be understood that, during the execution of step S12, if Figure 13 As shown, when using the first mask A'' to expose the first photoresist 103 (positive photoresist) on the polysilicon 102, the light-shielding patterns of the first mask A'' ( Figure 13 The shaded area in ) corresponds to the gates of ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention provides a transistor grid electrode array with different lengths and a preparation method thereof. According to the method, the exposure process is conduced on two set of masks, in the grid electrode array formed by exposing the first set of the masks, the two end of each grid electrode are flush in the vertical length direction and each grid electrode covers the corresponding grid electrode in a target array at least, in other words, the lengths of all the grid electrodes formed by exposure of the first set of the masks are the same, and the difference of the grid electrode widths after exposure and etching caused by the unequal lengths of the grid electrodes is reduced; the grid electrodes with the same length are made into the grid electrodes with the targeted lengths and the shapes by the adoption of the second set of the masks according to the lengths, due to the fact that the length dimensions of the grid electrodes are ordinarily larger than the width dimensions of the grid electrodes, the difference of the grid electrode lengths after exposure and etching does not exist basically. Accordingly, due to the fact that when the second set of the masks imaging is adopted, the widths of the grid electrodes have been defined by the first set of the masks, the precise control of the widths and the lengths of the grid electrodes is achieved, complex computing is not needed, and achievement is easy.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a transistor gate array with different lengths and a manufacturing method thereof. Background technique [0002] Transistor arrays are often involved in the semiconductor process, and in order to achieve different performances, the gate lengths of the transistors in the array are different. With the development of large-scale integrated circuits, the size of each device is gradually becoming smaller, coupled with the limitations of exposure limit and non-uniformity of layout density, in the same manufacturing process, the different gate lengths will lead to different gate lengths during exposure and etching. After completion, the gate width and the spacing between them deviate from the target size and spacing. [0003] In view of the above problems, the existing process generally adopts Optical Proximity Correction (Optical Proximity Correction, OPC) to reduce the opti...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28H01L29/423
CPCH01L21/28H01L29/401H01L29/423
Inventor 舒强祖延雷
Owner SEMICON MFG INT (SHANGHAI) CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap