Transistor gate array with different lengths and fabrication method thereof

Abstract

The invention provides a transistor grid electrode array with different lengths and a preparation method thereof. According to the method, the exposure process is conduced on two set of masks, in the grid electrode array formed by exposing the first set of the masks, the two end of each grid electrode are flush in the vertical length direction and each grid electrode covers the corresponding grid electrode in a target array at least, in other words, the lengths of all the grid electrodes formed by exposure of the first set of the masks are the same, and the difference of the grid electrode widths after exposure and etching caused by the unequal lengths of the grid electrodes is reduced; the grid electrodes with the same length are made into the grid electrodes with the targeted lengths and the shapes by the adoption of the second set of the masks according to the lengths, due to the fact that the length dimensions of the grid electrodes are ordinarily larger than the width dimensions of the grid electrodes, the difference of the grid electrode lengths after exposure and etching does not exist basically. Accordingly, due to the fact that when the second set of the masks imaging is adopted, the widths of the grid electrodes have been defined by the first set of the masks, the precise control of the widths and the lengths of the grid electrodes is achieved, complex computing is not needed, and achievement is easy.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a transistor gate array with different lengths and a manufacturing method thereof. Background technique [0002] Transistor arrays are often involved in the semiconductor process, and in order to achieve different performances, the gate lengths of the transistors in the array are different. With the development of large-scale integrated circuits, the size of each device is gradually becoming smaller, coupled with the limitations of exposure limit and non-uniformity of layout density, in the same manufacturing process, the different gate lengths will lead to different gate lengths during exposure and etching. After completion, the gate width and the spacing between them deviate from the target size and spacing. [0003] In view of the above problems, the existing process generally adopts Optical Proximity Correction (Optical Proximity Correction, OPC) to reduce the opti...

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Problems solved by technology

[0005] However, the above-mentioned optical proximity correction method involves a large amount of calculations, and different pattern layouts require different calculation processes, which is time-consuming and reduces the amount of deviation limited.

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