Manufacturing process of low dielectric constant film layer for microelectronic chip

Abstract

The invention discloses a preparation method of a low dielectric constant thin film layer. When the vacuum degree in a furnace body is smaller than 10-30 Pa, a radio-frequency power supply and a matcher are started; after a second mass flow meter is started, exhaust nitrogen used for emptying residual gas in the furnace body is fed in; octamethylcyclotetrasiloxane and cyclohexane are mixed uniformly and injected into a pressure-proof stainless steel kettle, a baffle valve is shut down manually, bubbling nitrogen and inert gas are injected respectively from a first gas inlet pipe and a second gas inlet pipe, sequentially flow through a first pressure-proof gas mixing tank, the pressure-proof stainless steel kettle and a first nozzle and are fed into the furnace body, accordingly the octamethylcyclotetrasiloxane and the cyclohexane are brought into the furnace body, and the octamethylcyclotetrasiloxane, the cyclohexane, the bubbling nitrogen and the inert gas deposit on the surface of a substrate to form the thin film layer under the plasma condition. According to the method, the dielectric constant value of a thin film is adjusted and controlled conveniently and precisely, the thin film layer with a low dielectric constant value is obtained, chemical components of the thin film layer are more uniform, the thin film layer has good thermostability and hardness, and flatness of the thin film is improved.

Description

technical field [0001] The invention relates to a manufacturing process of a low dielectric constant film layer for a microelectronic chip, belonging to the technical field of semiconductors. Background technique [0002] Inside the integrated circuit, the link between the various devices is mainly by metal wires. With the development of integrated circuit technology, the density of interconnection lines in the chip continues to increase, and the width and spacing of interconnection lines continue to decrease. The resulting parasitic effects of interconnection resistance (R) and capacitance (C) are becoming more and more obvious. . In order to reduce interconnect RC delay and improve chip performance, materials with low dielectric constant (k) have been continuously proposed and adopted, and have become the main development trend. [0003] The methods for preparing the low dielectric constant material layer generally include two methods: plasma enhanced chemical vapor depo...

AI Technical Summary

Problems solved by technology

[0004] Among many substances that can be used to prepare low dielectric constant materials, tetraethyl orthosilicate (TEOS) has been widely used as a common precursor of insulating materials in the early stage of integrated circuit development. Low, with the improvement of chip manufacturing level, the insulating material directly prepared by tetraethyl orthosilicate is more and more unsuitable as the insulating material in VLSI due to its high dielectric constant value. Therefore, more and more More and more researchers began to try to further reduce the dielectric constant value of the prepared material by changing the production process or adding other materials.

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