Method for improving the shape of side wall of through hole

Abstract

The invention provides a method for improving the shape of the side wall of a through hole. The method comprises the following steps: a silicon substrate is placed in a plasma etching chamber; reaction gases are bubbled into the plasma etching chamber, wherein the reaction gases include a fluorine-containing gas and one or two of COS and H2S; and carbon ions, oxygen ions, hydrogen ions and sulfide ions which are generated by COS or H2S are reacted with side wall silicon to produce a carbon-silicon compound, a silicon-oxide compound, a silicon-sulfur compound and a silicon-hydrogen compound, and the compounds are attached to the side wall and the bottom of a silicon through hole to form a passivation layer. An F plasma vertically bombards the passivation layer or Si at the bottom under high power, Si at the bottom of the hole can be quickly etched, and the F plasma etches the passivation layer at a low speed as the F plasma does not apply vertical kinetic energy force to the side wall of the hole. Therefore, in the whole etching process, the rate of lateral etching is low, and the aeolotropism is good.

Description

technical field [0001] The invention relates to the field of manufacturing semiconductor devices, in particular to the technical field of a method for improving the shape of the side wall of a through hole. Background technique [0002] In the past forty years, the research, development and production of microelectronic chips have been carried out along the prediction of Moore's Law; until 2008, companies such as Intel have begun to use 45nm to 50nm chips in the mass production of memory chips Line width processing technology. [0003] According to the prediction of Moore's Law, in order to further improve the integration level of the chip, it is necessary to use a processing technology with a line width of 32 nanometers or even 22 nanometers. However, the 32nm or 22nm processing technology not only encounters the limitations of lithography equipment and process technology, but also has unresolved problems such as cell stability, signal delay, and CMOS circuit feasibility. ...

AI Technical Summary

Problems solved by technology

During the alternating process of etching step and deposition step, the sidewall of the through hole is prone to surface with high roughness such as scallop, jagged or corrugated. As the depth continues to increase, the sidewall of the through hole is recessed toward the outside of the through hole, which leads to serious leakage of silicon via products; frequent switching of etching steps and deposition steps increases the difficulty of the through hole etching process and increases the processing cost

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