Small-scale high-speed large-dynamic digital receiver system and method

Abstract

The invention discloses a small-sized high-speed large dynamic digital receiver system and method. The receiver system comprises a digital analog conversion part and a signal extraction part; the digital analog conversion part adopts an ADC (analog to digital converter) chip; the output of the ADC chip is connected with an FPGA (field programmable gate array) chip logic functional module; the signal extraction part adopts an FPGA chip; the FPGA chip comprises and is sequentially provided with a data conversion module, two levels of FIFO (first in first out) modules, an FFT (fast Fourier transform) module and a super resolution compensation module; a gigabit Ethernet is connected to perform signal outputting after signal extraction. The realizing method of the small-sizes high-speed large dynamic digital receiver system comprises the steps of performing digital analog conversion on a radar simulation signal by the ADC chip, realizing the large dynamic wideband receiving and super resolution compensation processing by the FPGA chip, detecting and sorting the signals in the frequency band, and extracting one or more target signals. The small-sizes high-speed large dynamic digital receiver system is simple in structure, small in size, low in power consumption and strong in hardware reliability, can achieve 10bit sampling bit wide and 4GHz sampling rate, can be used for extracting one or more signals at the same time, and can be applied to multiple fields of radar countermeasure, remote sensing and the like.

Description

technical field [0001] The invention belongs to the technical field of signal processing, and further relates to a small-sized high-speed large-dynamic digital receiver system and method in the technical field of radar signal processing. It can be used in radar, missile, remote sensing and other fields for real-time data collection, sorting, extraction and processing. Background technique [0002] With the rapid development of large-scale integrated circuits and chip technology, receivers in systems such as communication, radar, and electronic countermeasures have been generally digitized. The function of the digital receiver is to receive the analog signal, sample and digitize it, and then extract the target signal through digital filtering and other methods. Therefore, it is extremely important to produce a digital receiver with small size, light weight, low power consumption, high sampling rate and large dynamic range for systems such as communication, radar and electron...

AI Technical Summary

Problems solved by technology

There are still deficiencies in this invention patent: First, because the system uses 16 AD converters to realize AD sampling digitization and uses three FPGAs to extract target signals, the system has complex structure, large volume and high power consumption

Second, since the system uses traditional reception methods, only one target signal can be received at a time

Again, the signal extraction of this system uses a digital down-conversion method, which requires a large amount of processing and low utilization of logic resources.

[0004] The main problems existing in the existing digital receivers are as follows: firstly, the structure of the receiver system is relatively complex, the volume is relatively large, and the power consumption is high

Secondly, only one signal can be processed at the same time. If two or more signals arrive at the receiver at the same time after being superimposed, it will not be possible to extract these multiple signals at the same time.

Thirdly, with the development of system imaging technology such as radar, the data rate, dynamic range, resolution and other technical indicators of existing receivers have become more and more difficult to meet the needs of subsequent signal processing

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