Back grid drain/source self-floating front grid N-MOSFET radio frequency switch zero-loss device based on SOI technology

Abstract

The invention discloses a back grid drain / source self-floating front grid N-MOSFET radio frequency switch zero-loss device based on the SOI technology. A drain area or a source area of an SOIPMOS device is transformed, the junction depth of the source area or the drain area is set to be slightly smaller than the thickness of P-type top layer silicon, the back grid drain semi-floatation serves as an example, the junction depth of the source area is large, the junction depth of the drain area is slightly smaller than the thickness of the P-type top layer silicon, a parasitic diode is formed, then isolation of a direct current signal is applied to a drain electrode, and a back grid MOSFET channel enters the conducting state due to biasing of a body grid and the back grid; as the back grid MOSFET operates in the conducting state, the impedance generated when a front grid MOSFET is located in the conducting state is adjusted, the radio frequency loss caused when a front grid N-MOSFET serves as a switch and is applied in the switch-on state is reduced, and even a zero-loss radio frequency switch is formed. When the self-heating effect of the device is generated and negative impedance of the back grid MOSFET is formed, or when the back grid MOSFET operates in an amplification state, coupling signals of the front grid can be directly amplified, energy losses caused when the front grid is in the opening state can be compensated, and the ultralow or zero loss radio frequency switch is formed.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, and relates to a back-gate-drain / source semi-floating front-gate N-MOSFET (N-type metal-oxide-semiconductor transistor) radio frequency switch zero-loss device based on SOI (semiconductor on insulating layer) technology. Background technique [0002] Due to the use of dielectric isolation, SOI NMOS devices eliminate the latch-up effect, and its unique insulating buried layer structure greatly reduces the parasitic effects of the device, greatly improves the performance of the circuit, and has small parasitic capacitance and high integration density. , high speed, simple process, small short channel effect and other advantages, it is widely used in low voltage, low power consumption, high speed, radiation resistance, high temperature resistance and other fields. The structure of a conventional SOI NMOS device is a sandwich structure of an insulating substrate, a buried layer, and a top mono...

AI Technical Summary

Problems solved by technology

When the SOI NMOS device works normally, the channel formed by source-drain conduction is only on the top surface of the P-type channel region, and it is a lateral channel, and the gate field plate covers the gate oxide layer, resulting in high on-state power consumption. , the working efficiency of the device is low, and the loss is large when used as a radio frequency switch, which is not conducive to improving the overall performance of the device and system

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