Semiconductor device manufacture method

Abstract

The invention provides a dummy structure manufacture method. The method comprises the following steps: forming an ONO (oxide-nitride-oxynitride) structure and a top amorphous silicon layer on a dummy gate material layer; etching the ONO structure by using the patterned top amorphous silicon layer as mask which can precisely control the size and profile morphology of the ONO structure and control the etching rate and thickness of each layer of the ONO structure, so that the ONO structure becomes the desired mask of the dummy gate material layer; and etching the dummy gate material layer by using the ONO structure as mask to realize precise pattern transfer, so that the key dimension and profile morphology of a dummy gate can be controlled precisely and the subsequently formed metal gate has good roughness, thereby ensuring the performance and stability of the device.

Description

technical field [0001] The invention relates to the field of semiconductor device manufacturing methods, in particular, to a dummy gate manufacturing method in a gate-last process. Background technique [0002] With the continuous shrinking of transistor size, HKMG (High-K insulating layer and metal gate) technology has become an essential technology for semiconductor processes below 45nm. In the HKMG technology, the Gate Last process (Gate Last) solution is widely favored by many well-known semiconductor companies in the industry. Among them, existing companies (such as Intel Corporation of the United States) have produced HKMG products based on the Gate Last process. The so-called gate-last process means that in the transistor manufacturing process, a dummy gate is first formed, and then, processes such as spacer deposition and etching, source-drain implantation and other processes are performed to form source-drain regions. After the fabrication of components other than ...

AI Technical Summary

Problems solved by technology

However, the existing gate-last process still has difficulties in the following problems, such as the formation of ultra-thin lines (below 45nm), the precise control of the critical dimension (Critical Dimension) and profile (Profile) of the gate, hard mask Sectional topography and remaining thickness control of structures, etc.

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