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Method for forming complementary metal oxide semiconductor tube

A technology of semiconductor tubes and oxides, which is applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of unstable performance of semiconductor tubes, and achieve the effect of stable threshold voltage and stable device performance

Active Publication Date: 2016-01-06
SEMICON MFG INT (SHANGHAI) CORP
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Problems solved by technology

[0005] However, the performance of CMOS transistors formed by existing technologies is not stable

Method used

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  • Method for forming complementary metal oxide semiconductor tube
  • Method for forming complementary metal oxide semiconductor tube
  • Method for forming complementary metal oxide semiconductor tube

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Embodiment Construction

[0031] As mentioned in the background art, the performance of CMOS transistors formed in the prior art is not stable.

[0032] The research of the inventors found that the material used to form the gate electrode layer of the complementary metal oxide semiconductor transistor in the prior art is aluminum, and when the aluminum material is deposited in the opening for forming the gate electrode layer, due to the deposition of the opening The size of the window is small and it is easy to generate defects. Therefore, after the deposition process, thermal annealing is required to reflow the liquid aluminum to make the formed gate electrode layer dense; however, the liquid aluminum during the thermal annealing process is easy to penetrate into the work function layer, and the work function of the aluminum is low; because in the prior art, the material of the gate electrode layer of the PMOS tube is the same as that of the gate electrode layer of the NMOS tube, when aluminum penetrat...

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Abstract

A forming method of a complementary type metal-oxide semiconductor tube comprises the following steps: providing a semiconductor substrate which comprises a first area and a second area, wherein the surface of the semiconductor substrate is provided with an insulating layer, the surface of the first area is provided with a first opening, the bottom of the first opening is provided with a first high-K dielectric layer, the surface of the first high-K dielectric layer is provided with a dummy gate layer, the surface of the second area is provided with a second opening, and the bottom of the second opening is provided with a second high-K dielectric layer; forming a second work function layer on the side wall of the second opening and the surface of the second high-K dielectric layer; forming a second gate electrode layer on the surface of the second work function layer, wherein the second gate electrode layer is made of copper; afterwards eliminating the dummy gate layer in the first opening; successively forming the first work function layer on the side wall of the first opening and the surface of the first high-K dielectric layer; and successively forming a first barrier layer and a first gate electrode layer on the surface of the first work function layer, wherein the first gate electrode layer is made of aluminum. The formed complementary type metal-oxide semiconductor tube has stable performance.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a complementary metal oxide semiconductor tube. Background technique [0002] Complementary Metal-Oxide-Semiconductor (CMOS) has become a commonly used semiconductor device in integrated circuits. The CMOS transistor includes: P-type metal oxide semiconductor (PMOS) and N-type metal oxide semiconductor (NMOS). [0003] In the prior art, in order to control the short channel effect while reducing the gate size, high-K dielectric materials are used to replace conventional silicon oxide and other materials to form gate dielectric layers, and metal materials are used to replace conventional polysilicon and other materials to form gate electrode layers; in addition , in order to adjust the threshold voltage of the PMOS tube and the NMOS tube, the existing technology will form a work function layer (work function layer) on the surface of the ga...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238
CPCH01L21/823864H01L29/66545
Inventor 平延磊周鸣王小娜
Owner SEMICON MFG INT (SHANGHAI) CORP
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