Method for preparing gate silicon oxide layers and method for processing semiconductor substrate

Abstract

The invention provides a method for preparing gate silicon oxide layers and a method for processing a semiconductor substrate. Nitrogen ions are injected into a low-pressure device area in advance and fluorine ions are injected in a high-pressure device area in advance, so that when the gate silicon oxide layers grow on the surface of the thermal oxidation semiconductor substrate, growth of the gate silicon oxide layers in the low-pressure device area is restrained, growth of the gate silicon oxide layers in the high-pressure device area is promoted, therefore, the gate silicon oxide layers with different thicknesses are formed, and the technological process is greatly simplified; further germanium and / or silicon is injected into the semiconductor substrate in a pre-non-crystallizing mode, and the channel carrier mobility is improved; in the annealing recrystallization process after non-crystallizing injection and nitrogen and fluoride ion injection, the characteristics of the surface of the silicon substrate are optimized, and the method is beneficial to improving the reliability of the gate oxide layers. The fabrication processing enables the peak value of the nitrogen concentration distribution of the low-pressure device area to be close to the surfaces of the gate silicon oxide layers, the follow-up boron penetration from P+ polycrystalline silicon can be effectively blocked, and the reliability of the thin gate silicon oxide layers in the low-pressure device area can be enhanced.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for preparing a gate silicon oxide layer and a method for processing a semiconductor substrate. Background technique [0002] With the rapid development of the microelectronics industry and ultra-large-scale integrated circuits (ULSI), the dual gate oxide process (Dual Gate Oxide, DGO) integrates high-voltage devices and low-voltage devices on the same chip, which is a breakthrough in the deep submicron integrated circuit manufacturing process The key process technology directly affects and determines the electrical characteristics and reliability of the device. It needs to grow gate silicon oxide layers of two thicknesses on the same chip at the same time to prepare transistors working at different voltages. [0003] Such as figure 1 As shown, in the prior art, in a CMOS high-voltage integrated circuit (High-Voltage Integrated Circuits, HVIC) compatible with...

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Problems solved by technology

However, in the current process, the peak of the nitrogen concentration distribution is always close to the interface between the gate silicon oxide layer and the substrate silicon, rather than the ideal distribution described above, such a distribution will reduce the mobility of carriers in the channel Rate

However, the commonly used double gate oxide process now generally grows the thick gate silicon oxide 104 and the first thin gate silicon oxide 103 in the high-voltage device regions II and III, and then grows the second thin gate silicon oxide in the low-voltage device region I. 102 (the thickness of the second thin gate silicon oxide 102 is relatively the smallest, the thickness of the first thin gate silicon oxide 103 is in the middle, and the thickness of the thick gate silicon oxide 104 is relatively the largest), and then the second thin gate silicon oxide 102 is nitrided , so that the nitrogen concentration distribution peaks in both thick and thin gate silicon oxides are on the side close to the silicon surface, which seriously affects the channel carrier mobility of both thick and thin gate transistors; at the same time, this dual The gate oxide process usually requires multiple thermal oxidation processes and multiple wet etching or self-aligned etching processes, making the process very complicated

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