Dynamic detection and execution method of program loop code based on instruction queue

Abstract

The invention discloses a dynamic detection and execution method of a program loop code based on an instruction queue. The dynamic detection and execution method comprises the implementation steps as follows: 1) instructions are taken from an instruction cache and stored in the instruction queue; the instructions stored in the instruction queue are sent to functional components for execution; when the execution instructions branch instructions and execution results are skip, skip directions and skip object distances are acquired; if the skip is backward and the skip object distances are within the length of the instruction queue, the next step is executed; 2) instructions corresponding to the program loop code are taken out from the instruction cache and filled in the instruction queue; and 3) the instruction cache is bypast, the instructions are taken out from the instruction queue and executed, and the working state of the instruction cache is restored after all the instructions of the program loop code are executed. The method has the advantages that the execution efficiency is high, the processing property is good, the execution power consumption is low, the hardware cost is low, the nesting loop is supported, the compatibility is strong, and the extendibility is good.

Description

technical field [0001] The invention relates to the field of microprocessor code execution methods, in particular to a dynamic detection and execution method of program loop codes based on instruction queues. Background technique [0002] There are generally a large number of loop codes in computer programs, which are used to represent operations that need to be repeated many times. Execution of loop code is repetitive behavior in a microprocessor, especially for instruction fetches where each fetch is the same address and the same instruction. In modern microprocessors, in order to alleviate the speed difference between the processor and external storage access (that is, the "storage wall" problem), a high-speed cache (ie cache) is integrated on-chip to save the memory required by the processor when it is running. instructions and data. The capacity of the high-speed cache is smaller than that of the external memory, and the reading and writing speed is fast. The read an...

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Problems solved by technology

However, this method needs to add an additional storage unit, and the length of the loop code that can be detected is limited by the storage capacity, especially in a multi-threaded processor, because each thread requires an independent instruction storage unit, so the additional Larger area overhead and poor scalability

Moreover, this method cannot dynamically complete cycle detection, which is not conducive to the compatibility of binary code

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