Method for manufacturing super-junction high-voltage power device

Abstract

The invention relates to a method for manufacturing a super-junction high-voltage power device. The method comprises the following steps of: providing an n-type heavy doping n+ substrate, forming an n-type epitaxial layer on the n+ substrate, and forming a p well region and a composite buffer layer; growing a field oxide layer on a silicon chip, defining an active region of the device, growing a gate oxide layer, and defining an area etched by polycrystalline silicon at the first time; performing deep p+ implantation on the surface of the whole semiconductor silicon chip, wherein a p+ area can be defined in a polycrystalline silicon area formed by the previous process; putting the silicon chip in polycrystalline silicon etching solution, performing secondary etching on the polycrystalline silicon by controlling the etching time and the etching rate, and forming an n-type source region n+; depositing a dielectric layer on the surface of the whole semiconductor silicon chip, defining a contact hole area, and etching the oxide layer; and depositing a metal layer, defining an etching area through photoetching, and performing metal etching. By the method, the avalanche tolerance of the device is improved, the reliability of the device is improved, and the threshold voltage and on-resistance of the device are not influenced.

Description

technical field [0001] The invention relates to a manufacturing method of a super-junction high-voltage power device. Background of the invention [0002] There is a parasitic NPN transistor in the MOSFET, such as figure 1 As shown, the resistance between the base and the emitter is equivalent to Rbb. When the power MOSFET is in the inductive load circuit, when the MOSFET is turned off from the on state to the instant off, the inductor releases the stored power to the MOSFET, and the base area has a current flow , The PN junction voltage drop Vbi=I*Rbb between the base and the emitter. When Vbi>0.7v, the parasitic triode will be turned on and the device will fail. One of the ways to prevent such failure is to reduce the base resistance Rbb. Reducing Rbb can be achieved by increasing the concentration of p-type impurities in the base region, but this usually affects the electrical properties of the device, which will increase the turn-on voltage and on-resistance of the...

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Problems solved by technology

[0006]In device manufacturing, the main production cost comes from the cost of the mask plate. The formation of the p+ region in the above two super-junction MOSFET manufacturing methods requires additional masks version to define the area of ​​the p+ region, which undoubtedly increases the manufacturing cost

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