GaN enhanced MIS-HFET device and preparation method of same

An enhanced, device technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as device reliability and stability, device threshold voltage that cannot meet the requirements of practical applications, and lattice damage , to achieve the effect of improving reliability and stability, increasing threshold voltage, and reducing access resistance

Active Publication Date: 2015-06-10
SUN YAT SEN UNIV
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  • Claims
  • Application Information

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Problems solved by technology

[0008] From the current research results, it is an ideal technical route to obtain GaN enhanced power devices by using the MIS-HFET structure, but the method of etching grooves in the gate area by ICP or implanting ions in the gate area, although It can make the device realize the normally-off characteristic, but it also brings the following problems: firstly, the threshold voltage of the device prepared by the above method cannot meet the requirements of practical application; The reliability and stability of the device affect the

Method used

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  • GaN enhanced MIS-HFET device and preparation method of same
  • GaN enhanced MIS-HFET device and preparation method of same
  • GaN enhanced MIS-HFET device and preparation method of same

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Embodiment 1

[0034] like Figure 9 Shown is a schematic structural diagram of the GaN enhanced MIS-HFET device of this embodiment, including a gate, a source, a drain, an insulating dielectric layer and a substrate 1 . The substrate usually chooses Si substrate or SiC substrate or sapphire substrate. A stress buffer layer 2 , a first GaN layer 3 and a selective growth layer are sequentially arranged on the substrate from bottom to top, and the selective growth layer includes a second GaN layer 7 and a heterogeneous layer 8 thereon. Wherein the first GaN layer is a high resistance GaN layer. The middle part of the selective growth layer has a through groove channel, and the bottom surface of the groove channel is covered with a p-type GaN layer 6 , the thickness of the p-type GaN layer 6 is less than or equal to the thickness of the second GaN layer 7 . Both sides of the upper surface of the heterogeneous layer 8 are covered with ohmic contact metal to form source and drain respectively. ...

Embodiment 2

[0047] like Figure 10 As shown, it is a schematic diagram of another structure of the GaN enhanced MIS-HFET device of the present invention, which is basically the same as the device structure of Example 1, the only difference is that when the heterogeneous layer is selectively grown, by modulating the N-type doping, That is, an N-type doped heterogeneous layer 13 is formed to further reduce the ohmic contact resistance of the source and drain regions and increase the current density of the device.

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Abstract

The invention relates to the technical field of semiconductor devices, and in particular relates to a GaN enhanced MIS-HFET (Metal Insulator Semiconductor Heterojunction Field Effect Transistor) device and a preparation method of the same. The device provided by the invention comprises a grid electrode, a source electrode, a drain electrode, an insulating dielectric layer and a substrate, wherein the substrate is orderly provided with a stress buffer layer, a first GaN layer and a selective growing layer from top to bottom, and the selective growing layer comprises a second GaN layer and a heterogeneous layer thereon; the middle part of the selective growing layer comprises a through groove channel, the bottom surface of the groove channel is covered by a p type Gan layer, and the thickness of the p type GaN layer is not more than that of the second GaN layer; two sides of the upper surface of the heterogeneous layer are coved by ohmic contact metals to respectively form the source electrode and the drain electrode, the insulating dielectric layer covers the upper surface of the device except for the positions of the source electrode and the drain electrode, and the grid electrode covers the groove channel on the insulating dielectric layer. The GaN enhanced MIS-HFET device is simple in manufacturing technology and high in device stability, and simultaneously, by the preparation method, the threshold voltage of the device is improved.

Description

technical field [0001] The invention relates to a semiconductor device and a preparation method thereof, in particular to a GaN enhanced MIS-HFET device used in high-temperature and high-power switching devices and a preparation method thereof. Background technique [0002] GaN-based wide-bandgap semiconductors have the characteristics of high breakdown electric field, high electron saturation drift rate and high thermal conductivity, and the use of heterostructures can form a high-concentration two-dimensional electron gas. These advantages make GaN in the field of high-power electronic devices There are very broad application prospects. [0003] In practical applications, enhanced power devices can meet the "fail-safe" requirements. However, due to the polarization effect of GaN, a high-concentration two-dimensional electron gas is formed at the interface of the AlGaN / GaN heterostructure, making the device directly fabricated by the AlGaN / GaN heterostructure a depletion-...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/778H01L21/335
Inventor 刘扬张金城贺致远张佰君
Owner SUN YAT SEN UNIV
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