Output buffer

Abstract

The invention discloses an output buffer which comprises a level conversion module, a preceding-stage drive module and an output module, wherein the level conversion module is used for generating a first logic signal with a first level range and a second logic signal with a second level range according to an input signal; the preceding-stage drive module is composed of a low-voltage transistor and is used for generating a first control signal and a second control signal according to the first logic signal and the second logic signal; the output module is used for generating an output signal with a third level range according to the first control signal and the second control signal; and the size of either of the first level range and the second level range is smaller than the size of the third level range.

Description

technical field [0001] The invention relates to an output buffer, especially an output buffer with low output jitter. Background technique [0002] Please refer to figure 1 , figure 1 It is a schematic diagram of an output buffer 10 in the known technology. The output buffer 10 can generally be applied to applications that need to output voltage signals to the outside of the IC, for example, on a system-on-a-chip (SoC), so as to send the output signal to such as a dynamic random access memory (DRAM). Dynamic Random Access Memory, DRAM) and other memory devices required signal drive circuit. Such as figure 1 As shown, the output buffer 10 generally includes a logic AND (AND) gate 100, level conversion units 102, 104, pre-stage drive units 110, 112, parallel output transistor arrays 120_1~120_M, 122_1~122_M and resistors 130. And the gate 100 performs a logic "AND" operation on an enable signal OE and a data signal DATA, so as to determine whether to transmit the data si...

AI Technical Summary

Problems solved by technology

Under the trend of reducing the power supply voltage level of the output stage, the driving current of the high-voltage transistor will be weakened accordingly, resulting in a large signal delay time

At the same time, the low operating voltage is relatively unfavorable against the noise generated during synchronous operation from the power supply

As a result, the output signal OUT will have a large output jitter

Images