Clock pulse width modulation circuit and clock pulse width modulation method

Abstract

The invention provides a clock pulse width modulation circuit and a clock pulse width modulation method. In the invention, an edge in one clock period of an output clock signal is generated by tracking one edge in one clock period of a to-be-modulated clock period, and another edge in one clock signal of the output clock signal is modulated directly by an initialized modulation circuit so as to obtain the output clock signal. The technical scheme provided by the invention can provide the output clock signal with high accuracy, low jitter and short locking time for a high-speed analog / digital conversion system on the premise of ensuring small chip area occupied by the modulation circuit.

Description

technical field [0001] The present invention relates to the technical field of clock pulse width modulation, in particular to a clock pulse width modulation method and a clock pulse width modulation circuit. Background technique [0002] In the case of the development of very large scale integration (VLSI) towards high speed and low voltage, many high-speed analog-to-digital (A / D) converters use double data rate technology to obtain greater data throughput. Among them, pipeline Analog-to-digital converters are favored by many designers for their high-speed and high-precision features. In the design of pipeline analog-to-digital converters, the accuracy and jitter characteristics of the clock signal duty cycle have an increasing impact on the conversion accuracy of the circuit system with the increase in frequency and conversion bits, and the clock that provides high-precision duty cycle and low jitter Signals are even more important. Clock pulse width modulation technology...

AI Technical Summary

Problems solved by technology

[0010] The invention provides a clock pulse width modulation circuit and a clock pulse width modulation method, which solve the technical problems of long modulation time of clock signal and large jitter of output clock signal in the prior art

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