Preparation method of semiconductor device

Abstract

The invention discloses a preparation method of a semiconductor device. The preparation method comprises the following steps of: providing a semiconductor substrate on which a metal interconnecting wire is formed; forming a dielectric layer on the surface of the semiconductor substrate; forming a nitrogen doped silicon carbide layer, an oxide layer and a hard mask layer on the surface of the dielectric layer in sequence; carrying out dry etching on the hard mask layer, the oxide layer, the nitrogen doped silicon carbide layer and the dielectric layer so as to form an opening at the position corresponding to the metal interconnecting wire; carrying out wet cleaning on the semiconductor substrate. According to the preparation method, the nitrogen doped silicon carbide layer is used for replacing the traditional Octamethyl cyclotetrasiloxane layer so that the nitrogen doped silicon carbide layer is prevented from being corroded excessively, thereby improving the reliability of the semiconductor device.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a manufacturing method of a semiconductor device. Background technique [0002] With the further shrinking of the feature size of semiconductor devices, the RC delay of the interconnection line has gradually become the main contradiction affecting the circuit speed. In order to improve this, the process method of making the metal interconnection line structure from metal copper has been adopted. Compared with the traditional aluminum process, the advantage of the copper process is that it has lower resistivity and better conductivity, and the interconnection wires made of it can be made smaller while maintaining the same or even stronger current carrying capacity. more dense. In addition, it also has greater advantages over aluminum processes in terms of electromigration, RC delay, reliability, and lifetime. [0003] For details, please refer to Figure 1A-1E , w...

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Problems solved by technology

[0009] However, it is found in actual production that since the octamethyltetrasilane layer 130 is relatively loose, the etching rate of the cleaning liquid for the patterned hard mask layer 150' and the dielectric layer 120 is relatively slow, while for the patterned The etch rate of the octamethyltetrasilane layer 130' is relatively fast, so that the patterned octamethyltetrasilane layer 130' is over-etched, resulting in a recess in the sidewall of the opening 121 (such as Figure 1E shown by the dotted line)

This will make it difficult for the metal to fill into the recess in the subsequent copper electroplating process, which will lead to the failure of the electromigration test and affect the reliability of the semiconductor device.

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