Acid corrosion technology for 8-inch single crystal silicon chip for insulated gate bipolar transistor (IGBT)

Abstract

The invention relates to an acid corrosion technology for an 8-inch single crystal silicon chip for an insulated gate bipolar transistor (IGBT). An acid corrosion solution for acid corrosion of the single crystal silicon chip in the technology comprises 49 percent hydrogen fluoride, 63 percent HNO3 and 96 percent CH3COOH which are mixed in a ratio of 1: (1.8-4.3): (1.0-5.8); the temperature of the acid corrosion solution is 16 to 23 DEG C; the circulating volume of the acid corrosion solution is 180 to 400 L; and after a batch of single crystal silicon chips are subjected to acid corrosion, the discharge flow of the acid corrosion solution is 2 to 5L, and the liquid supply amount of the acid corrosion solution is 1 to 4L. By adopting the technology, the 8-inch acid corrosion silicon chip with the total thickness variation (TTV) added value of less than 1.5 microns, the total indicator reading (TIR) added value of less than 1.5 microns, good surface and the removal amount scatter difference of less than 1 micron can be stably and massively produced, the qualification rate of the silicon chip is over 98 percent, and the requirement for the high-quality 8-inch single crystal silicon chip for the IGBT device is met.

Description

technical field [0001] The invention relates to a production method of a single crystal silicon chip, in particular to an acid etching process for an 8-inch single crystal silicon chip for IGBT. Background technique [0002] As we all know, the larger the diameter of the silicon wafer, the more semiconductor devices can be integrated into each silicon wafer, and the lower its cost, so as large-scale integrated circuits and semiconductor discrete devices, especially IGBT (insulated gate bipolar transistor) ) The raw material of epitaxial wafers - silicon polished wafers, also has a tendency to develop to large sizes. At present, 8-inch polished wafers occupy the mainstream position in the international polished silicon wafer market, accounting for about 40-50%. But so far, most domestic enterprises produce silicon polishing wafers of 6 inches and below. Only a few enterprises in Beijing can produce polishing wafers of 8 inches and above, but their production capacity and qua...

AI Technical Summary

Problems solved by technology

[0004] But unfortunately, the current domestic acid etching process has limitations. It is difficult to control the geometric parameters of the etched silicon wafer surface such as TTV (total thickness variation) and TIR (flatness); The removal amount of silicon wafers is often different, and even the thickness of silicon wafers after the same round of corrosion is also very different, so the thickness of silicon wafers after corrosion is large. Catalyst HNO produced 2 And if the heat of reaction cannot be "blown away" in time, the local reaction rate will be accelerated, resulting in differences in the amount of removal

Using the existing process to etch 8-inch silicon wafers, due to the large surface area of ​​the silicon wafers, the removal amount of different silicon wafers and different positions of the same silicon wafer varies greatly, and the limitations of the technical indicators after etching are more prominent, such as 8-inch heavy doping The TTV increase value before and after As silicon wafer etching is about 8 μm, and the TIR increase value is about 4 μm. The thickness difference of the silicon wafer etched in the same round is relatively large, about 2.5-3 μm, which cannot meet customer requirements; in addition, some silicon wafers such as crystal For and heavily doped silicon wafers, flower or ring-shaped and strip-shaped surface morphology defects are easily formed on the surface after etching