Method for manufacturing semiconductor device

Abstract

The invention discloses a method for manufacturing a semiconductor device. The method comprises the following steps of: firstly, forming a contact hole etching stop layer which is prepared from boron-doped amorphous carbon, fluorine-doped amorphous carbon, chlorine-doped amorphous carbon or amorphous carbon; secondly, depositing a medium layer on the contact hole etching stop layer, and etching the medium layer and stopping etching on the upper surface of the contact hole etching stop layer to form a groove; and finally, incinerating the contact hole etching stop layer in the groove to form a contact hole. By the method, the damage to the semiconductor device in the process of etching the contact hole can be avoided.

Description

technical field [0001] The invention relates to semiconductor technology, in particular to a manufacturing method of a semiconductor device. Background technique [0002] Figure 1 to Figure 17 It is a process cross-sectional schematic diagram of a manufacturing method of a semiconductor device in the prior art, and the method mainly includes: [0003] Step 101, see figure 1 A semiconductor substrate 1001 is provided, and an N well 1002 , a P well 1003 and a shallow trench isolation region (STI) 1004 are formed on the semiconductor substrate 1001 . [0004] First, the active regions of the N-type metal oxide semiconductor (NMOS) tube and the P-type metal oxide semiconductor (PMOS) tube are defined by using a double well process, thereby obtaining the N well 1002 and the P well 1003, and then, through photolithography and An STI 1004 is formed on the semiconductor substrate 1001 through etching and other processes, and the STI 1004 is used to electrically insulate the acti...

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Problems solved by technology

[0040] However, in the above step 115, since the thickness of the contact hole etch stop layer 1013 is relatively thin, if the dielectric layer 1014 and the contact hole etch stop layer 1013 have a relatively low etching selectivity ratio, then in step 116, when the When the dielectric layer 1014 is etched, it is easy to etch directly to the etch stop layer 1013 of the contact hole and continue to etch below the etch stop layer 1013, thereby causing damage to the gate structure below the contact hole 1015. It can be seen that, In order to avoid damage to the semiconductor device, under the premise that the thickness of the contact hole etch stop layer 1013 is relatively thin, the dielectric layer 1014 and the contact hole etch stop layer 1013 are required to have a high etching selectivity ratio, but the prior art still has no corresponding solution

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