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Resistance control method for nonvolatile variable resistive element

A technology of non-volatile and resistive elements, which is applied in the field of resistance control of non-volatile variable resistive elements, can solve the problems of slow forming time and no progress of forming process, etc., and achieve the perfect writing and erasing work The effect of shortening the time and shortening the molding time

Inactive Publication Date: 2012-02-08
SHARP KK
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0015] The result is slower forming times, or the forming process no longer progressing

Method used

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  • Resistance control method for nonvolatile variable resistive element
  • Resistance control method for nonvolatile variable resistive element
  • Resistance control method for nonvolatile variable resistive element

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no. 1 Embodiment approach

[0045] Figure 5 It is a circuit configuration diagram of a nonvolatile semiconductor memory device to which the present invention is applied (hereinafter referred to as "the device 1 of the present invention"). Such as Figure 5 As shown, the device 1 of the present invention is configured to include: a memory cell array 501 (501a or 501b, referred to as 501a in this embodiment), a control circuit 502, a voltage generating circuit 504, a first selection line decoder 506, and a first selection line decoder 506. 2 Select line decoder 508.

[0046] memory cell array 501a with image 3The equivalent circuit diagram of FIG. 2 shows a memory cell array in which a plurality of memory cells including nonvolatile variable resistance elements and selection transistors are arranged in a matrix in the row and column directions. Here, the nonvolatile variable resistive element is a two-terminal type nonvolatile variable resistive element in which electrodes are carried on both ends of ...

no. 2 Embodiment approach

[0071] In the above-mentioned first embodiment, the case where the method of the present invention is applied to the memory cell array 501a in which the second selection line and the third selection line are perpendicular to each other has been described in detail, but the method of the present invention is not controlled by the memory cell array. The structure limits its application. Hereinafter, a case where the method of the present invention is applied to the memory cell array 501b in which the second selection line and the third selection line extend in parallel will be described in detail.

[0072] memory cell array 501b with Figure 8 The equivalent circuit diagram of FIG. 2 shows a memory cell array in which a plurality of memory cells including nonvolatile variable resistance elements and selection transistors are arranged in a matrix in row and column directions, respectively. The configurations of the nonvolatile variable resistance element and the selection transi...

no. 3 Embodiment approach

[0090] The method of the present invention becomes more effective when applied to a nonvolatile semiconductor device including a forming sensing circuit that senses a change in potential of the second selection line or the third selection line accompanying the forming completion. Figure 9 It is a circuit configuration diagram of a nonvolatile semiconductor memory device (hereinafter referred to as "the device 3 of the present invention") to which the method of the present invention is applied. Such as Figure 9 As shown, the device 3 of the present invention is between the second selection line and the second selection line decoder 508 in the device 1 of the present invention including the memory cell array 501a or 501b (501a in this embodiment). The structure of the shape sensing circuit 510 is also provided.

[0091] The shaping sensing circuit 510 is disposed, for example, between the second selection line and the second selection line decoder 508, and, during the shaping...

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Abstract

A resistance control method for a nonvolatile variable resistive element is provided. The method realizes synchronous progress of writing, wiping and forming processing of a plurality of memory cells. The device includes a memory cell array in which the unit memory cells having nonvolatile variable resistive elements and transistors are arranged in a matrix. The memory cells that are targets of a memory operation are selected by first selection lines (word lines), second selection lines (bit lines) and third selection lines (source lines). The method includes steps of selecting one or more first selection lines, selecting a plurality of second selection lines, and applying a compensated voltage in which a change in potential of the third selection lines caused by current flowing into the third selection lines through the second selection lines is compensated in a voltage that is necessary for the memory operation, such that the voltage necessary for the memory operation is applied to all of the selected memory cells.

Description

technical field [0001] The present invention relates to any memory operation for collectively writing, erasing or shaping a plurality of nonvolatile variable resistance elements in a nonvolatile semiconductor memory device for storing information. Resistance control method of non-volatile variable resistance element. Background technique [0002] In recent years, FeRAM (Ferroelectric RAM, ferroelectric random access memory), MRAM (Magnetic RAM, magnetic random access memory), OUM (Ovonic Unified Memory, phase change memory) and other device structures, from the viewpoint of high performance, high reliability, low cost, and process integration , is undergoing fierce development competition. However, each of these current memory devices has advantages and disadvantages, and the ideal of a "universal memory" that combines the advantages of SRAM, DRAM, and flash memory is still far away. [0003] For these prior arts, a resistive nonvolatile memory RRAM (Resistive Random Acce...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/02G11C16/24
CPCG11C13/0007G11C13/0023G11C13/0069G11C13/0097G11C2013/0083G11C2013/0088G11C2213/79
Inventor 石原数也
Owner SHARP KK
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