Electrostatic discharge test structure and system of gate-driven MOSFET (metal oxide semiconductor field effect transistor)

Abstract

The invention discloses an electrostatic discharge test structure of a gate-driven MOSFET (metal oxide semiconductor field effect transistor). The structure comprises an MOSFET and an adjustable resistor, wherein the gate of the MOSFET is connected with a gate bonding pad; the source of the MOSFET is connected with a source bonding pad; the adjustable resistor is connected between the gate bonding pad and the source bonding pad; and the resistance value of the adjustable resistor connected to the electrostatic discharge test structure of the gate-driven MOSFET is adjusted according to the requirement on gate offset. The invention also discloses an electrostatic discharge test system of the gate-driven MOSFET. According to the structure and system disclosed by the invention, the space occupied by the electrostatic discharge test structure of the gate-driven MOSFET and the system in the layout design can be effectively reduced, and the layout design efficiency for the electrostatic discharge test structure of the gate-driven MOSFET and the system is improved.

Description

technical field [0001] The present invention relates to the field of semiconductor technology, in particular to a gate-driven metal oxide semiconductor field effect transistor (MetatOxide Semiconductor Field Effect Transistor, hereinafter referred to as: MOSFET) electrostatic discharge (Electrostatic Discharge) test structure and system. Background technique [0002] Complementary Metal-Oxide-Semiconductor (hereinafter referred to as CMOS) technology has entered the sub-micron era, but the subsequent complexity of advanced process development has brought a lot to improve the robustness of ESD networks. difficulty. In order to solve this problem in the prior art, the robustness of the electrostatic discharge network is usually improved by adopting gate-driven technology, but the gate-driven technology needs to generate gate bias, so it needs to be solved in the layout design and development process. The problem of how to effectively generate the gate bias effect due to the g...

AI Technical Summary

Problems solved by technology

In turn, the designer chooses the resistance value carefully and conservatively in order to save the layout space when selecting the resistance value, which is also unfavorable to the layout design of the MOSFET electrostatic discharge test structure

[0005] In the prior art, in the layout design process of the electrostatic discharge test structure of the MOSFET using the gate drive technology, the electrostatic discharge test structure of the MOSFET that produces the gate bias effect has the following types: The first electrostatic discharge test structure of the gate drive MOSFET is Apply gate bias directly on the MOSFET, and this ESD test structure is difficult to implement due to technical difficulties, so it is rarely used

The second electrostatic discharge test structure of the gate-driven MOSFET is to connect a resistor in series between the gate and the source, and generate a gate bias through the gate-drain capacitive coupling effect. The problem of inefficiency

Adopting this technical scheme, the resistors in the ESD test structure of each gate drive MOSFET will occupy a large layout space in the entire gate drive MOSFET ESD test system, resulting in a waste of layout space

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