Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Method for manufacturing gate oxide

A technology of gate oxide layer and fabrication method, which is applied in semiconductor/solid-state device manufacturing, electrical components, semiconductor devices, etc., can solve the problems of product reliability, increase in surface roughness of semiconductor substrates, etc., to ensure device performance and process. simple effect

Inactive Publication Date: 2012-10-31
SEMICON MFG INT (SHANGHAI) CORP
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In the process of removing the first gate oxide layer 102 in the second region by a wet process, the etchant of the wet etching process includes ammonium fluoride and hydrofluoric acid, and its pH value ranges from 2 to 8, preferably 6. to 8, this is because the use of the etchant can have a larger process window to prevent the photoresist layer 103 from peeling off during the wet etching process, but the etchant will cause Increased surface roughness of semiconductor substrates, resulting in product reliability issues

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for manufacturing gate oxide
  • Method for manufacturing gate oxide
  • Method for manufacturing gate oxide

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0016] A method for controlling the thickness of a gate oxide layer in a logic region according to the present invention, as shown in FIG. 16 , includes: step S101, providing a semiconductor substrate including a first region and a second region, and forming a ratio of A first gate oxide layer with a predetermined thickness of 10 angstroms to 100 angstroms; step S102, forming a photoresist layer on the first gate oxide layer in the first region, using the photoresist layer as a mask, and using a pH value at 2 to 8 wet etching reagents to remove part of the first gate oxide layer on the semiconductor substrate in the second region, and the remaining first gate oxide layer in the second region after etching has a thickness in the range of 10 to 20 angstroms; step S103 , removing the photoresist layer; step S104, using a wet etchant with a pH value of 2 to 6, to remove the remaining first gate oxide layer in the second region; step S105, forming a first gate oxide layer on the fir...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a method for manufacturing a gate oxide. The method comprises the following steps: providing a semiconductor substrate containing a first region and a second region, and forming a first gate oxide which is 10 to 100 angstroms thicker than the preset thickness on the semiconductor substrate; forming a photoresist layer on the first gate oxide of the first region, and removing part of the first gate oxide on the semiconductor substrate of the second region by using the photoresist layer as a mask and adopting a wet etching reagent with the pH value of 2-8 to ensure that the thickness of the etched residual first oxide of the second region is within a range of 10-20 angstroms; removing the photoresist layer; removing the residual first gate oxide of the second region by adopting the wet etching reagent with the pH value of 2-6; and forming a second gate oxide on the first region of the semiconductor region.

Description

technical field [0001] The invention relates to a manufacturing process of a semiconductor device, in particular to a method for manufacturing a gate oxide layer. Background technique [0002] With the rapid development of semiconductor manufacturing technology, in order to achieve faster computing speed, larger data storage capacity and more functions, semiconductor chips are developing towards higher device density and high integration. A semiconductor device generally includes a core device as a memory and a peripheral circuit as a logic device, and its manufacturing method is as follows. First, a semiconductor substrate is provided, and the semiconductor substrate includes a first region and a second region, wherein the first region It is usually used to form the gate oxide layer of the logic device area, and the second area is usually used to form the gate oxide layer of the memory cell area. Because the operating voltage of the logic device area is high, the thickness ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28H01L21/283
Inventor 林德成袁馨
Owner SEMICON MFG INT (SHANGHAI) CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products