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High speed serializer/deserializer transmit architecture

A converter and flip-flop technology, applied in the field of communication systems, can solve the problems of increasing waveforms, increasing the waiting time of pipeline triggers, etc.

Inactive Publication Date: 2009-09-16
QUALCOMM INC
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  • Summary
  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Conventional SerDes have the following disadvantages: they use first-in-first-out (FIFO) circuits to span clock domains, thus requiring additional power and area; they use high-speed multiplexers to manage bit selection for output paths, which adds additional complexity to the waveform. asymmetry, or adding additional pipeline trigger latency

Method used

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  • High speed serializer/deserializer transmit architecture
  • High speed serializer/deserializer transmit architecture
  • High speed serializer/deserializer transmit architecture

Examples

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Embodiment Construction

[0013] Various embodiments will now be described with reference to the drawings, wherein like reference numerals are used to represent like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. It may be evident, however, that the embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing one or more embodiments.

[0014] In one embodiment, the parallel-to-serial converter circuit 100 includes an figure 1 The following circuit is depicted in:

[0015] Pipeline Input Stage 110: This is a set of registers that enables easy timing closure of data bits from the core to the MDDI Host PHY. It fetches 8 bits of parallel data from the core and latches them using the core byte_clock. The first host and the external host have ...

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Abstract

A Serializer / Deserializer (100; 400) apparatus comprises a serializer (100; 400) adapted to take N parallel bits of data and shifts them out serially at N times a clock speed to a transmitter, a transmitter enable block (110, 120, 420) adapted to start the serializer means, and a count block (130; 430). The serializer comprises flip-flops and muxes, and is adapted to N parallel bits of data and shifts them out serially at N times a clock speed to a transmitter. The transmitter enable block (110, 120; 420) comprises an inverter and flip-flops, and is adapted to start the serializer. The count block may comprise a counter or an inverter, f lip-flops,, and a NOR gate, and is adapted to create a divided clock which programs data loading in the serializer.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of US Provisional Application No. 60 / 865,606, filed November 13, 2006, entitled "LOW LATENCY, LOWPOWER, FIFO INDEPENDENT, HIGH SPEED SERDE STRANSMITARCHITECTURE." This application is hereby incorporated by reference in its entirety. technical field [0003] The present invention relates generally to communication systems and, more particularly, to serializer / serializer (SerDes) circuits for use in communication systems. Background technique [0004] Generally, the SerDes circuit is incorporated into an integrated circuit and operates at a high speed, and converts parallel data into serial data and serial data into parallel data. [0005] Conventional SerDes have the following disadvantages: they use first-in-first-out (FIFO) circuits to span clock domains, thus requiring additional power and area; they use high-speed multiplexers to manage bit selection for output paths, which adds ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M9/00H03K5/135
CPCH03M9/00H03K5/135
Inventor J·冈萨雷斯
Owner QUALCOMM INC
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