Asynchronous pulse synchronizer

Abstract

The invention provides an asynchronous pulse synchronizer. The asynchronous pulse synchronizer comprises an input logic unit, a meta-stable elimination unit and an output logic unit; the input logic unit is used for flattening pulse signals of an input clock domain into level signals, wherein an exclusive or gate and a D trigger are included; the meta-stable elimination unit comprises three D triggers; and the output logic unit is used for converting the level signals of an output clock domain into the pulse signals, wherein an exclusive or gate and a D trigger are included. The asynchronous pulse synchronizer provided by the invention can convert the pulse signals of a clock domain into the pulse signals of another asynchronous clock domain in digital circuit cross-clock-domain design; and furthermore, the meta-stable state of the signals in a synchronous process can be prevented.

Description

technical field [0001] The invention belongs to the field of digital circuits, in particular to an asynchronous pulse synchronizer in a digital circuit. Background technique [0002] With the increase of the complexity of the current SOC design, the problem of multi-clock domain design is an inevitable problem in the current SOC design. If the logic is not clearly thought out during design, this problem can only be found in the post-simulation stage, which will increase the number of design iterations and prolong the design cycle. [0003] Metastability is the failure of a flip-flop to reach an identifiable state within a specified period of time. When a flip-flop goes metastable, there is no way to predict the cell's output level, nor when the output will settle to a certain correct level. During this stable period, the flip-flop outputs some intermediate level, or possibly oscillates, and this unwanted output level can cascade down the signal path to each flip-flop. [...

AI Technical Summary

Problems solved by technology

When a flip-flop goes metastable, there is no way to predict the output level of the unit, nor when the output will stabilize at a certain correct level

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