Method for preparing nano CMOS integrated circuit by SiN masking technique

An integrated circuit and nanoscale technology, applied in the manufacture of circuits, electrical components, semiconductors/solid-state devices, etc., can solve problems such as rising production costs, restricting the development of the semiconductor industry, waste of resources and energy, etc., to improve manufacturing capabilities and achieve leapfrogging Type development, the effect of small conductive channel

Inactive Publication Date: 2010-04-07
XIDIAN UNIV
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  • Description
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  • Application Information

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Problems solved by technology

After years of accumulation, the world has invested more than one trillion US dollars in equipment and technology in the microelectronics industry. If the process technology is improved only through the replacement of equipment, a generation of equipment will be eliminated every 18 months, which will cause huge losses. The waste of resources and energy leads to an increase in production costs. Therefore, this situation seriously restricts the development of the semiconductor industry

Method used

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  • Method for preparing nano CMOS integrated circuit by SiN masking technique
  • Method for preparing nano CMOS integrated circuit by SiN masking technique
  • Method for preparing nano CMOS integrated circuit by SiN masking technique

Examples

Experimental program
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Effect test

Embodiment 1

[0030] Embodiment 1: prepare the CMOS integrated circuit that conduction channel is 45nm on Si substrate, concrete steps are as follows:

[0031] Step 1, depositing a masking layer, as shown in Figure 2(a).

[0032] (1a) Select the crystal orientation as and the doping concentration as 10 15 c m-3 Left and right p-type Si substrate sheets 1;

[0033] (1b) Thermally oxidize a layer of SiO with a thickness of 40 nm on the substrate 2 buffer layer 2;

[0034] (1c) on SiO 2 A 100nm-thick SiN layer 3 is deposited on the buffer layer by low-pressure chemical vapor deposition (LPCVD) for masking of well implantation.

[0035] Step 2, forming a well region, as shown in FIG. 2(b).

[0036] (2a) Photoetching the P well region 4 and the N well region 5 on the SiN layer 3 according to the phase sequence;

[0037] (2b) Boron is implanted in the P well region to form a p-type region, and SiO is thermally oxidized on the surface of the P well region 2 , while advancing the P well, f...

Embodiment 2

[0065] Embodiment 2: prepare the CMOS integrated circuit that conduction channel is 65nm on SOI substrate, concrete steps are as follows:

[0066] Step 1, depositing a masking layer, as shown in Figure 2(a).

[0067] (1a) Select the crystal orientation as and the doping concentration as 10 15 cm -3 left and right p-type SOI substrates 1;

[0068] (1b) Thermally oxidize a layer of SiO with a thickness of 40 nm on the substrate 2 buffer layer 2;

[0069] (1c) on SiO 2 A 100nm-thick SiN layer 3 is deposited on the buffer layer by means of APCVD for the masking of the implantation in the well region.

[0070] Step 2, forming a well region, as shown in FIG. 2(b).

[0071] (2a) Photoetching the P well region 4 and the N well region 5 on the SiN layer 3 according to the phase sequence;

[0072] (2b) Boron is implanted in the P well region to form a p-type region, and SiO is thermally oxidized on the surface of the P well region 2 , while advancing the P well, forming a P wel...

Embodiment 3

[0100] Embodiment 3: prepare the CMOS integrated circuit that conduction channel is 90nm on Si substrate, concrete steps are as follows:

[0101] Step 1, depositing a masking layer, as shown in Figure 2(a).

[0102] (1a) Select the crystal orientation as and the doping concentration as 10 15 cm -3 Left and right p-type Si substrate sheets 1;

[0103](1b) Thermally oxidize a layer of SiO with a thickness of 40 nm on the substrate 2 buffer layer 2;

[0104] (1c) on SiO 2 A 100nm thick SiN layer 3 is deposited on the buffer layer by plasma-enhanced chemical vapor deposition (PECVD) for masking implantation in the well region.

[0105] Step 2, forming a well region, as shown in FIG. 2(b).

[0106] (2a) Photoetching the P well region 4 and the N well region 5 on the SiN layer 3 according to the phase sequence;

[0107] (2b) Boron is implanted in the P well region to form a p-type region, and SiO is thermally oxidized on the surface of the P well region 2 , while advancing ...

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Abstract

The invention discloses a method based on SiN masking technique for fabricating a nano-scale CMOS integrated circuit. The process includes the following steps: fabricating an N / P well and growing a Poly-Si / SiN / Poly-Si multi-layer structure on the N / P well; etching the top layer of Poly-Si into a window and then depositing a layer of SiN; etching away the SiN on the surface of the substrate, exceptthe SiN at the side wall of the Poly- Si; based on the etching ratio of Poly-Si to SiN(11:1), etching the Poly-Si on the surface of SiN; etching the SiN on surface of the substrate, except the SiN onthe side wall of the SiN so as to expose the substrate of Poly-Si; based on the etching ratio of Poly-Si to SiN, etching the Poly-Si, except the Poly-Si in the protective area on the side wall of SiNsoas to form an n / p MOSFET grid, and depositing a layer of SiO2 at the well area; injecting ions, self-aligning, and forming the source area and the drain area of the n / p MOSFET grid so as to form an n / p MOSFET device; and photoetching interconnection lines of the device so as to form a CMOS integrated circuit with a conducting channel at 45-90nm. The method can fabricate a CMOS integrated circuit which is improved in performance by 3-5 generations on a micron-scale Si integrated circuit processing platform without adding any funds and equipment investment.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a method for manufacturing nanoscale Si integrated circuits by using the existing micron-scale Si integrated circuit manufacturing process. Background technique [0002] The information industry is the pillar industry of the national economy, and it serves all fields of the national economy. Microelectronics technology is the key to the information industry, and integrated circuits are the key among the keys. Since the advent of integrated circuits in 1958, they have developed at an astonishing speed. They have become the core of information science and technology, the cornerstone of national economic development and national defense construction, and have had a huge impact on world politics, economy and culture. As the fastest-growing, most influential, and most widely used technology in human history, integrated circuits have become an impo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238
Inventor 胡辉勇张鹤鸣戴显英宋建军舒斌宣荣喜赵丽霞王晓燕秦珊珊
Owner XIDIAN UNIV
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