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Array processor structure

A technology of array processors and processor units, applied in architecture with multiple processing units, electrical digital data processing, instruments, etc., can solve the problems of DSP waste, difficult to determine the number of DSPs, high research and development costs, etc., and achieve data transmission Flexible, easy to implement quickly, and short design cycle

Inactive Publication Date: 2008-12-10
PEKING UNIV SHENZHEN GRADUATE SCHOOL
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Problems solved by technology

However, because the function of DSP is too powerful in this solution, the number of DSPs is not easy to determine. One DSP may not meet the design requirements, and two or more DSPs may be wasteful. To meet the differences in the application of different algorithms, it is necessary to change the overall structure of the hardware during design, which is not easy to implement quickly, and cannot meet the needs of rapid product launch. Multiple R&D tape-outs lead to a longer design cycle, so the design and development costly

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Embodiment Construction

[0025] The features and advantages of the present invention will be described in detail with reference to the accompanying drawings.

[0026] Such as figure 1 As shown, the array processor structure includes multiple processor units and multiple routing units (marked by R in the figure), and the processor unit in this embodiment adopts DSP (marked by D in the figure). Each DSP is a DSP array with a square grid structure arranged in rows and columns adjacent to each other through an interconnection bus, and each routing unit R is also arranged in a row and column adjoining a square grid structure routing array through an interconnection bus , its rows and columns are distributed alternately with the rows and columns of the DSP array. In one embodiment, each DSP has five input / output ports, and the input / output ports of the DSPs on the non-array boundary are five, four of which are connected to the corresponding ports of the adjacent four DSPs, and the remaining One connects t...

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Abstract

The present invention discloses an array processor structure, which comprises a plurality of processor units for forming a processor array. The adjacent processor units are connected with an interconnected bus. The present invention also comprises at least a router unit and each router unit is respectively connected with at least two processor units through the interconnected bus. The router unit receives the data packet transmitted by a source processor unit and transmits the data volume in the data packet to an object processor unit through a transmission path according to the addressing information of the object processor unit attached in the data packet. The present invention can support the achievement of ASIC chip in different calculations through configuring the scale and function of processor and router units.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, in particular to an array processor structure. Background technique [0002] The current integrated system chip is mainly composed of three parts: one or more CPUs carrying the operating system, several standard I / O interfaces, and an ASIC (Application Specific Integrated Circuit) that supports specific algorithm processing. The complexity of chip design and the difference in functions are mainly determined by ASIC, because its design will not only affect the system architecture of the entire chip, but will definitely affect the design time and cost. The current ASIC design is mainly to design a corresponding ASIC circuit for a certain algorithm, or to use one or more DSPs (digital signal processors, that is, digital signal processors) to complete the calculation function of the algorithm. Taking the ASIC structure implemented by DSP as an example, the specific algorithm ASIC circuit can...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/80G06F13/38G06F9/445
CPCG06F15/16
Inventor 王新安戴鹏黄维刘彦亮叶兆华周丹魏来
Owner PEKING UNIV SHENZHEN GRADUATE SCHOOL
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