Semiconductor storing device, semiconductor device, storing system and renovating control method

Abstract

A semiconductor memory device includes a memory cell array, wherein the memory cell is divided into a plurality of memory bodies; caches, each of which is used to store data of word line selected by line address; set registor, for setting data retention capacity so as to ensure a retention region for storing data during self-refresh cycle and a non retention region for non storing data during self-refresh cycle locate in a same memory bank; a refresh controller, for exporting refreshing line address with prescribed distance during self refreshing cycle and implementing refreshing operation to selective word line corresponding to the line address in enabled memory bank; and memory bank controller, for activating the memory bank when the selected work line is included in the retention region, and activating all memory banks when the selected work line is included in the non retention region.

Description

technical field [0001] The present invention relates to a refresh technology for a semiconductor memory device such as a DRAM (Dynamic Random Access Memory), and more particularly, to a method for refreshing a set partial area in a memory cell array for reducing current consumption in a standby mode technology of the partial array self-refresh method. Background technique [0002] In recent years, there has been a tendency to mount large-capacity DRAMs in mobile devices such as mobile phones. In order to achieve low power consumption when the mobile device is in standby mode, it is necessary to reduce the current consumption in the self-refresh operation of the DRAM. Therefore, a partial array self-refresh method (hereinafter referred to as "PASR") has been proposed (see, for example, Japanese Patent Application Laid-Open No. 2004-11 8938). According to PASR, in a memory cell array generally including a plurality of banks, a self-refresh operation is selectively performed ...

AI Technical Summary

Problems solved by technology

However, PASR needs to be set such that all banks can be flushed to maximize cache capacity, and thus cannot reduce current consumption in standby mode

Thus, there arises a problem that in the existing DRAM, it is difficult to realize the maximization of the cache capacity of all the banks and the reduction of the current consumption in the PASR

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