Digital low-converter

Abstract

The invention discloses a digital down converter which comprises a signal input end which is used for receiving input signals and a signal output end which is used for outputting signals, wherein, N independent operation branches are arranged between the signal input end and the signal output end; each operation branch comprises an extractor the extraction factor of which is N, a multiphase branch mixer which is constructed according to an N-phase digital mixer, and a multiphase branch filter which is constructed according to an H(z) expression of an N-phase digital filter which are connected with each other in order; input ends of extractors of various operation branches are coupled with the signal input end; outputs of branch filters of various operation branches are outputted to the signal output end through addition by an adder; an i operation branch corresponding to the input signals comprises i-1 clock cycle time delays; N and i are all natural numbers, and i is more than or equal to 1 and less than or equal to N. Arithmetic speed of each operation branch is lowered to be 1 / N of the prior arithmetic speed, and modules for improving the arithmetic speed do not exist because each operation branch is completely independent, thereby processing difficulty of a system is reduced.

Description

technical field [0001] The invention relates to a digital down converter. Background technique [0002] The IF digital receiver is required to be able to realize real-time demodulation of Quadrature Phase-Shift Keying (QPSK) signals with a bandwidth of 100MHz to 200MHz, an IF of 375MHz, and a sampling rate of 500MSPS. In this case, the bandpass sampling theorem can no longer be used. At present, there is no field-programmable gate array (Field-Programmable Gate Array, namely FPGA) chip that can work above 500MHz. In this way, the operating frequency is less than 200MHz after layout and routing. Therefore, parallel algorithms must be used to decompose the amount of computation before real-time processing is possible. For cost considerations, Xilinx's low-cost FPGA is used for verification, which is more limited in speed and scale. [0003] Generally, digital receivers lower the signal to a relatively low intermediate frequency before sampling and demodulating. When the int...

AI Technical Summary

Problems solved by technology

Therefore, there will still be a speed bottleneck in the connection between the polyphase mixer and the polyphase filter

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