Making method for silicon germanium extension layer

Abstract

The invention provides a method for manufacturing a silicon germanium epitaxial layer. The method includes: carrying out the first selective epitaxial growth process under the first condition, and the processing time accounts for 1%-20% of the total process time of the silicon germanium epitaxial layer. Then, a second selective epitaxial growth process is carried out under the second condition, and its processing time accounts for 99%-80% of the total processing time of the SiGe epitaxial layer. Wherein, the first condition and the second condition include temperature condition or pressure condition, and the reaction gases used in the first selective epitaxial growth process and the second selective growth process include at least silicon-containing gas and germanium-containing gas.

Description

technical field [0001] The invention relates to a method for forming a semiconductor structure, and in particular to a method for forming a silicon germanium epitaxial layer by a selective epitaxial growth process. Background technique [0002] When the semiconductor integrated circuit enters the deep sub-micron (Deep Sub-Micron) process, the size of the components is gradually reduced, so that the operating speed of the entire integrated circuit will be effectively improved. However, when the size of the device is further reduced, in the case of a metal oxide semiconductor transistor (MOS transistor), the resistance and parasitic capacitance of the gate and source / drain will increase accordingly, making the device smaller The resulting improvement of the overall circuit performance is hindered. If the device size continues to shrink, the area of ​​the entire device will be occupied by the source / drain ohmic contact (ohmic contact), thus setting the upper limit of the integ...

AI Technical Summary

Problems solved by technology

[0004] However, if the uniformity of the silicon germanium epitaxial layer is not good, it will cause the problem of pattern loading effect, which makes the subsequent process difficult to control and affects the yield of the process.

Furthermore, if the selective epitaxial growth process for the silicon germanium epitaxial layer is not properly controlled, it is easy to form the silicon germanium epitaxial layer at an unintended location (that is, the selection margin is small), or the growth rate of the silicon germanium epitaxial layer is slow and the yield is low. low level problem

What's more, it will destroy the insulating spacer interface of the metal oxide semiconductor transistor

Images