Plasma flat panel display driving chip structure and method for preparing the same

Abstract

The present invention discloses a driving chip structure of plasma plate display and its processing method, and is applied to column-location-selection driving chip and line-scanning driving chip of the plasma plate display. The chip structure includes P-type substrate, N-type epitaxial layer set on the P-type substrate, high-pressure-P-type, high-pressure-N-type and low-pressure-complementary-type lateral MOS transistors set on the N-type epitaxial layer, N-type-heavy-doped-buried-layer-and-high-pressure-P-type lateral MOS transistor set between the P-type substrate and the N-type epitaxial layer. The high-pressure-N-type and low-pressure-complementary-type lateral MOS transistors are set above the N-type-heavy-doped buried layer. The structure and its processing method of the present invention are based on epitaxial material, and there is a big cost advantage comparing with it of using SOI.

Description

technical field [0001] The invention relates to a plasma flat panel display (PDP) drive chip structure and a preparation method thereof, which are suitable for a column address selection drive chip of a plasma flat panel display and a row scanning drive chip of a plasma flat panel display. Background technique [0002] The plasma flat panel display driver chip is controlled by low-voltage logic to realize high-voltage output. With the continuous improvement of display technology and driving technology, the plasma flat panel display driver chip has the following development trends: the operating frequency of the column address selection driver chip is continuously improved, and the integration level is continuously improved; is also continuously increasing. Currently commonly used plasma flat panel display drive chip structures and preparation methods include: (1) epitaxial process structure, integrating high-voltage nVDMOS, high-voltage pLDMOS and low-voltage CMOS, using de...

AI Technical Summary

Problems solved by technology

The third process is limited by the withstand voltage of the device itself and the isolation structure, so it is not suitable for the up-scan driver chip above 100V.

Although the first two processes are suitable for row scanning driver chips and column addressing driver chips, both processes also have their own shortcomings: the isolation structure area of ​​the epitaxial process structure is too large, and the area of ​​the chip used for isolation exceeds 20%; SOI process structure, although the isolation area is small, less than 5% of the chip area, but the cost of SOI materials (over 7um epitaxy) that meets the requirements will be several times that of epitaxy materials, and domestic manufacturing capacity is seriously insufficient

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