Digital phase locked loop

Abstract

The invention relates to a digital phase locked loop (PLL) 12 for demodulating an intermediate frequency signal. The digital phase locked loop12 comprises two coordinate rotation digital computers 24 and 30 in its phase detector. The robustness of the PLL 12 can be improved by means of a gain control circuit 27, a sign detector 20, a carrier monitoring circuit 28 and an adjustable loop filter 32.

Description

technical field [0001] The present invention relates to a digital phase-locked loop (PLL) for demodulating amplitude modulated signals, and more particularly, the invention relates to a phase-locked loop for an intermediate frequency modulator for a broadcast signal, such as a television signal, which has a digital phase comparison A circuit, a digital loop filter and a digital controllable oscillator, the phase comparison circuit includes a digital mixer and a phase shift circuit. Background technique [0002] Common digital phase-locked loops are often used to demodulate modulated signals, in which case the transmitted information signal is demodulated from the modulated carrier signal by means of a PLL. Broadcast signals, especially television signals, are often modulated by AM. Accordingly, PLLs are used in receiver circuits in order to identify information-carrying signals from AM-IF by means of synchronous demodulation using carrier regeneration. [0003] The digital...

AI Technical Summary

Problems solved by technology

[0006] However, common IF demodulators have proven to be unstable in daily operation, in particular because of low signal strength, unwanted FM / PM modulation, poor signal Noise ratio and static carrier frequency error

Therefore, the conclusion is that the traditional PLL may be unstable or not provide any stable demodulation results

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