Semiconductor integrated circuit

Abstract

Disclosed herein is a semiconductor integrated circuit, wherein a desired circuit is formed by combining and laying out a plurality of standard cells and connecting the cells together, of which the cell length, i.e., the gap between a pair of opposed sides, is standardized, the plurality of standard cells forming the desired circuit include complementary in-phase driven standard cells, each of which includes a plurality of complementary transistor pairs that are complementary in conductivity type to each other and have their gate electrodes connected together, and N (≧2) pairs of all the complementary transistor pairs are driven in phase, and the size of the standardized cell length of the complementary in-phase driven standard cell is defined as an M-fold cell length which is M (N≧M≧2) times the basic cell length which is appropriate to the single complementary transistor pair.

Description

[0001]The present application is a reissue application of application Ser. No. 12 / 805,158, now U.S. Pat. No. 8,357,955, issued Jan. 22, 2013. The present invention contains subject matter related Japanese Patent Application JP 2009-198547 filed in the Japan Patent Office on Aug. 28, 2009, the entire contents of which being incorporated herein by reference. BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a semiconductor integrated circuit having a desired circuit formed by combining and laying out a plurality of standard cells each having transistors and gate electrodes and connecting the cells together.[0004]2. Description of the Related Art[0005]In a common standard cell, at least one of the sizes thereof in the directions orthogonal to each other (so-called vertical and horizontal directions) is standardized to a few types or, for example, to three types. The so-called vertical size is referred to as the height of the standard cell....

AI Technical Summary

Benefits of technology

The patent text describes a semiconductor integrated circuit that has a layout design that reduces wasted space and lowers costs. The circuit contains standard cells for driving multiple complementary transistor pairs in phase. By integrating the gate electrodes of these transistors into a common gate line, the circuit reduces the number of internal wirings required to achieve in-phase driving. The circuit also utilizes a power line sharing structure with adjacent single still cells, which further reduces wasted space and lowers costs. Overall, the patent provides a solution for designing highly efficient semiconductor circuits that meet the needs of small-scale and resource-sensitive applications.

Problems solved by technology

However, there are cases in which the single height configuration is not suitable depending on the circuit scale.

However, several gate lines must be further shorted together.

As result, it may be impossible to secure a space to connect the gates together with the upper layer wirings.

Even if a space is secured, it may be necessary to design wirings that are bent in a complex manner, thus resulting in reduced workability for design and mask preparation and leading to higher cost.

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