Heterojunction bipolar transistor and semiconductor integrated circuit device using the same
a semiconductor integrated circuit and bipolar transistor technology, applied in the direction of semiconductor devices, basic electric elements, electrical apparatus, etc., can solve the problems of avalanche breakdown, low breakdown voltage, and high-frequency characteristics of transistors, so as to achieve effective restraint of avalanche breakdown, the effect of raising or improving the breakdown voltag
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first embodiment
[0056]FIG. 5 shows the layered structure of a npn-type heterojunction bipolar transistor 50 according to a first embodiment of the invention.
[0057]As shown in FIG. 5, the transistor 50 comprises a semi-insulating GaAs substrate 3, a n+-type GaAs sub-collector layer 4 (thickness: 500 nm) formed on the substrate 3, and a n-type InGaP collector layer 9 (thickness: 100 nm) formed on the layer 4. The surface of the sub-collector layer 4 is partially exposed from the overlying collector layer 9. A collector electrode 31 is formed on the exposed part of the layer 4.
[0058]The n+-type GaAs sub-collector layer 4 is doped with silicon (Si) as a n-type dopant at a doping concentration of 4.0×1018 cm−3. The n-type InGaP collector layer 9 has a composition ratio of In (i.e., XIn) of 0.48 and thus, it is expressed as In0.48Ga0.52P. However, the In composition ratio XIn may be set at a value in the range from 0.48 to 0.5. The n+-type InGaP collector layer 9 is doped with Si as a n-type dopant at a ...
second embodiment
[0089]FIG. 11 shows the layered structure of a npn-type heterojunction bipolar transistor 50A according to a second embodiment of the invention.
[0090]With the above-described heterojunction bipolar transistor 50 according to the first embodiment of FIG. 5, the high-electric field part is generated in the n+-type InGaP collector layer 9. However, if the doping concentration of the n+-type GaAs sub-collector layer 4 is insufficient, the depletion layer formed in the collector region (i.e., in the collector layers 7, 8, and 9) will expand to the inside of the sub-collector layer 4. In this case, high electric field will be generated in the depleted part of the layer 4. Accordingly, to make sure that the advantages of the invention are obtainable, it is preferred that a semiconductor layer having a wider energy band gap than the collector layer 7 is additionally provided on the side of the sub-collector layer 4 to be adjacent to the collector layer 9. The transistor 50A of the second em...
third embodiment
[0097]FIG. 12 shows the circuit diagram of a semiconductor integrated circuit device (IC) 60 according to a third embodiment of the invention. This IC or device 60 is applicable to high-output amplifier IC for microwaves.
[0098]As shown in FIG. 12, the IC 60 comprises an amplifier 17a and an amplifier 17b serially connected to each other by way of an impedance-matching circuit 18 located therebetween. These elements 17a, 17b and 18 are located between a RF (Radio-Frequency) input terminal 19 and a RF output terminal 20. A bias circuit 21 supplies specific bias voltages to the amplifiers 17a and 17b.
[0099]The amplifier 17a, which is located on the input terminal side, is in a driver amplifier stage. The amplifier 17a comprises a plurality of the heterojunction bipolar transistors 50 or 50A according to the first or second embodiment, where the total emitter area of the transistors 50 or 50A used is set at 960 μm2. The amplifier 17b, which is located on the output terminal side, is in...
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