Semiconductor memory structure and method for preparing the same

Abstract

The present disclosure provides a semiconductor memory structure including a substrate, a plurality of first trenches disposed in the substrate, a plurality of second trenches disposed in the substrate and spaced apart from the first trenches, a plurality of buried digit lines disposed in the first trenches, and a plurality of buried word lines disposed in the second trenches. The first trenches include a first depth, and the second trenches include a second depth. The second depth of the second trenches is greater than the first depth of the first trenches. Top surfaces of the buried word lines are lower than bottom surfaces of the buried digit lines.

Description

PRIORITY DATA[0001]This patent claims the benefit of U.S. Provisional Patent Application Ser. No. 62 / 610,264 tiled Dec. 25, 2017, the entire disclosure of which is hereby incorporated by reference.TECHNICAL FIELD[0002]The present disclosure relates to a semiconductor memory structure and a method for preparing the same, and more particularly, to a semiconductor dynamic random access memory (DRAM) structure and a method for preparing the same.DISCUSSION OF THE BACKGROUND[0003]Electrical products are becoming lighter, thinner, shorter, and smaller, and DRAMs are being scaled down to match the trends of high integration and high density. A DRAM including many memory cells is one of the most popular volatile memory devices utilized today. Each memory cell includes a transistor and at least a capacitor, wherein the transistor and the capacitor form a series connection with each other. The memory cells are arranged into memory arrays. The memory cells are addressed via a word line and a d...

AI Technical Summary

Benefits of technology

The present patent describes a method for making a semiconductor memory structure using two etching processes. This method reduces both word line to word line and digit line to digit line capacitance, and helps increase device density by vertical structures. The arrangement of the buried word lines and digits lines, along with the isolation structures, also reduces word line disturbance. In summary, this patent provides a technique for improving the performance of semiconductor memory structures.

Problems solved by technology

However, as the reduction of the device size also reduces the distance between the word lines and the bit lines, word line disturbance is observed in adjacent word lines.

When the word line disturbance becomes serious, performance of the DRAM cell is degraded.

In contrast, with a comparative DRAM memory structure, pairs of word lines that share one digit line also share the same channel region, and thus always suffer from word line disturbance.

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