Grapho-epitaxy dsa process with dimension control of template pattern
a grapho-epitaxy and template pattern technology, applied in the field of semiconductor processing, can solve the problems of high defect level, large resist feature size, and inability to form high-resolution mandrels
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[0020]The present principles provide methods for forming templates with improved dimensional control. The templates may be provided for directed self-assembly (DSA) applications. In particularly useful embodiments, a dielectric stack is etched to form template lines. A substantially unreactive spacer is formed on sides of the template lines, which is employed to provide critical dimension control of the template line. DSA material is introduced between the spacers of the template lines and processed. A reactive ion etch (RIE) process may be employed to remove the spacers to provide an image reversed etch pattern for further etching, e.g., of a substrate or underlying layers.
[0021]In accordance with the present principles, an optical planarization layer (OPL) / silicon antireflection coating (ARC) stack may be patterned and combined with unreactive spacers (e.g., formed from a hydrophobic material with minimal hydroxyl groups) along sides of patterned stack. The patterned stack with sp...
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