Low external resistance etsoi transistors

Abstract

A disposable dielectric structure is formed on a semiconductor-on-insulator (SOI) substrate such that all physically exposed surfaces of the disposable dielectric structure are dielectric surfaces. A semiconductor material is selectively deposited on semiconductor surfaces, while deposition of any semiconductor material on dielectric surfaces is suppressed. After formation of at least one gate spacer and source and drain regions, a planarization dielectric layer is deposited and planarized to physically expose a top surface of the disposable dielectric structure. The disposable dielectric structure is replaced with a replacement gate stack including a gate dielectric and a gate conductor portion. Lower external resistance can be provided without impacting the short channel performance of a field effect transistor device.

Description

BACKGROUND[0001]The present disclosure relates to semiconductor structures, and particularly to extremely thin semiconductor-on-insulator (ETSOI) field effect transistors having low external resistance, and methods of manufacturing the same.[0002]Extremely thin semiconductor-on-insulator (ETSOI) devices have been proposed to enable continued scaling of complementary metal-oxide-semiconductor (CMOS) devices with superior short channel characteristics at sub-20 nm gate lengths so that enhanced gate control can be provided to a thin semiconductor channel having a thickness not greater than 30 nm. However, high external resistance, i.e., high source / drain resistance, adversely impacts the performance of ETSOI field effect transistor by limiting the on-current. This problem is caused by the limited thickness of a top semiconductor layer, as well as by dopant leaching from the extension regions into a buried oxide layer. In order to enhance the performance of ETSOI field effect transistor...

AI Technical Summary

Benefits of technology

The patent describes a method of forming a disposable dielectric structure on a semiconductor substrate, followed by the replacement of the structure with a replacement gate stack for better performance. The method allows for the removal of the disposable structure without affecting the short channel performance of a field effect transistor device and also provides lower external resistance.

Problems solved by technology

However, high external resistance, i.e., high source / drain resistance, adversely impacts the performance of ETSOI field effect transistor by limiting the on-current.

This problem is caused by the limited thickness of a top semiconductor layer, as well as by dopant leaching from the extension regions into a buried oxide layer.

Images