Digital phase locked loop having insensitive jitter characteristic for operating circumstances
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[0041]Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First of all, we should note that in giving reference numerals to elements of each drawing, like reference numerals refer to like elements even though like elements are shown in different drawings. In describing the present invention, well-known functions or constructions will not be described in detail since they may unnecessarily obscure the understanding of the present invention. It should be understood that although exemplary embodiment of the present invention are described hereafter, the spirit of the present invention is not limited thereto and may be changed and modified in various ways by those skilled in the art.
[0042]FIG. 2 is a block diagram of a digital phase locked loop according to the present invention.
[0043]The digital phase locked loop according to the present invention basically includes a time-to-digital converter (TDC) 10, a ...
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