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Device for polishing the edge of a semiconductor substrate

a technology for polishing devices and semiconductor substrates, applied in edge grinding machines, manufacturing tools, lapping machines, etc., can solve problems such as deformation of planarity

Inactive Publication Date: 2010-07-29
S O I TEC SILICON ON INSULATOR THECHNOLOGIES
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0014]The curved cross section has the advantage that the protruding residual topography can be removed over its entire radial extent so that a double side polishing step, like used in the prior art, is no longer necessary. This has the particular advantage that due to the use of the device according to the invention, a polishing process that consumes less material compared to the known process applying DSP can be carried out. At the same time, polishing using a curved pad has the further advantage that the cross section can be chosen such that the geometry of the substrate, in particular in the edge region, can be kept constant meaning that, in case the substrate is reused, the quality of the products achieved out of recycled substrate remains stable. As a consequence the reclaiming process can be carried out faster and at less cost.
[0029]Further preferred, the method can comprise a de-oxidation step to remove any oxide present on the protruding topography. This further facilitates the polishing process.

Problems solved by technology

Indeed, in the case of DSP the wafer is floating between two polishing pads, whereas in case of CMP the wafer is fixed to a support on the backside which may induce mechanical constraints during polishing and thus lead to a degraded planarity.

Method used

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  • Device for polishing the edge of a semiconductor substrate
  • Device for polishing the edge of a semiconductor substrate
  • Device for polishing the edge of a semiconductor substrate

Examples

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first embodiment

[0043]FIG. 3 illustrates pad holder 7 and polishing pad 9 according to the invention. Here both elements are illustrated as one unit. The cross sectional view illustrated in FIG. 3 is the same as the one illustrated in FIG. 2.

[0044]The cross section of pad holder 7 / polishing pad 9 has a concave shaped part 21 facing the substrate 5 positioned on the substrate holder 3. In the lateral direction, thus in the radial direction r in FIG. 2 of substrate 5, the pad holder 7 / polishing pad 9 has its concave portion 21 extending over at least a width w1 corresponding to the width w2 of the edge portion of substrate 5 that carries the protruding residual topography 23 (see also FIG. 1). Typically, the width w2 is of the order of 1.5 mm so that w1 is also of at least 1.5 mm.

[0045]According to the variant, the width w1 is chosen to be at least 3 mm. In this case it becomes possible to remove also the protruding topography in the notch region of a semiconductor wafer.

[0046]The concave shape 21 of...

third embodiment

[0052]FIG. 5 illustrates the pad holder 7″ and polishing pad 9″. The shape of the cross section facing the substrate 5 positioned on substrate holder 3 has a plane part 51 positioned between two convex parts 53, 55. This shape is specially adapted to remove the step 23 in the edge region of substrate 5, in particular when it is associated with a vertical movement along arrow 57 controlled by control unit 11, which is illustrated in FIG. 2. This embodiment has the advantage that it is easy to realize. It can be associated with an additional edge polishing step to remove the unwanted parts positioned above the predetermined splitting area 27 on the side of substrate 5.

fourth embodiment

[0053]FIG. 6 illustrates a pad holder 7′″ and polishing pad 9′″ which combines a central concave portion 61 and two convex portions 63, 65 and the side facing the surface 15 of the substrate 5. In this embodiment, with one translational direction along arrow 67 or 69, thus along a vertical direction or an oblique direction, the desired final shape of substrate 5 can be achieved with one polishing step, in particular also on the side 25 of substrate 5, so that an additional edge polishing step becomes obsolete. Furthermore, due to the smooth transition between the concave and convex portions, the transition between the area with the step 23 and the area on the surface of substrate 5 without step 15 (where detachment occurred), is also smooth.

[0054]All embodiments of the invention have the advantage that the undesired protruding residual topography in the peripheral region of the substrate can be completely removed. As a consequence a double-sided polishing, like in the prior art, is ...

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Abstract

Disclosed are devices and methods for chemical and mechanical polishing of the edge of a semiconductor substrate that includes a protruding residual topography in a peripheral region of the substrate resulting from a layer transfer process based on an ion implantation step, a bonding step and a detachment step, such as Smart-Cut™. To be able to remove this step-like region, exemplary devices include a polishing pad, wherein the polishing pad is arranged and configured such that its cross section in a plane perpendicular to the surface of a substrate holder is curved. The disclosure furthermore relates to a pad holder used certain exemplary devices and methods for polishing a semiconductor substrate that has a protruding residual topography.

Description

CROSS REFERENCE TO RELATED APPLICATION[0001]This application claims priority to European Patent Application No. EP09290064.6, filed Jan. 29, 2009. The aforementioned patent application is incorporated herein by reference in its entirety.BACKGROUND[0002]1. Field of the Disclosure[0003]The present disclosure relates to, for example, a device for polishing the edge of a semiconductor substrate that has a protruding residual topography in a peripheral region of the substrate resulting from a layer transfer including an ion implantation step. The present disclosure also relates to a polishing pad used in such a device and a method for reclaiming a surface of a semiconductor substrate that has a protruding residual topography.[0004]2. Description of Related Art[0005]The so-called Smart Cut™ process, illustrated in FIG. 1 provides high quality silicon on insulator (SOI) substrates. During this process, two substrates, called a handle substrate 101 and a donor substrate 103, usually a silic...

Claims

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Application Information

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IPC IPC(8): B24B9/06B24B7/20B24B37/04
CPCB24B9/065B24B37/042H01L21/76254H01L21/02032H01L21/02079B24B37/28H01L21/302
Inventor SCHWARZENBACH, WALTERKERDILES, SEBASTIENALAMI-IDRISSI, AZIZ
Owner S O I TEC SILICON ON INSULATOR THECHNOLOGIES
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