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Nonvolatile semiconductor memory device and method of manufacturing nonvolatile semiconductor memory device

Inactive Publication Date: 2010-04-01
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Benefits of technology

[0008]However, the present inventor has recognized the following point. Namely, the technique disclosed in JP-A-2005-228786 has the following problems. When the gate (word gate) 122 and the diffusion layer electrodes 132 are silicided (to form the silicide layers 134 and 135), the memory gate insulating film (charge storage layer) 114 which is the ONO film already has a section of an upper end exposed. When a silicide step is performed while the section of the ONO film is being exposed in this way, a silicide film is formed in the ONO film because nickel components attached onto the nitride film of the ONO film are easily subjected to a silicide reaction with silicon in the nitride film. Then, even when the excessive nickel components are removed by etching, the silicide film is not removed, and remains on the ONO film. As a result, the silicide layer (control gate) 124 and the gate (word gate) 122 may be short-circuited due to the remaining silicide film. A technique for preventing short-circuiting between the ONO film and the control gate is desired.
[0009]Additionally, in this structure, the silicide layer (control gate) 124 which is the silicide film is in direct contact with the memory gate insulating film (charge storage layer) 114 serving as a charge storage region. That is, nickel silicide which has an extremely low resistance as compared to polysilicon, comes into direct contact with the ONO film. Thus, it is thought that charges stored in a nitride film of the ONO film are very easily affected by an electric state of the nickel silicide (for example, variations in voltage), or a state of an oxide film (for example, uniformity in film thickness) located on the nickel silicide side of the ONO film. Thus, the electric state and the film thickness state can make the state of charges stored in the nitride film extremely unstable, and make the distribution of charges nonuniform. In particular, nickel components of the nickel silicide may be partly diffused into the oxide film on the nickel silicide side to degrade the quality of the ONO film. In that case, the charges stored in the nitride film can be prone to penetrate the nickel components. In this way, such occurrence of unstable charges and nonuniform electrolytic distribution at the ONO film, and degradation in quality of the ONO film leads to a crash of data, which may significantly reduce reliability and stability of a memory cell. Thus, there is a need for a technique that prevents the instability of charges and nonuniformity of electrolytic distribution at the ONO film and the degradation in quality of the ONO film, thereby to enhance the reliability and stability of the memory cell.
[0012]In this exemplary embodiment, the silicide layer is provided by silicide containing nickel. Therefore, the resistance of the control gate can be made lower. On the other hand, the non-silicide layers are provided between the silicide layer and the charge storage layer, thereby separating both layers. Thus, even when a nitride film exposed to the section of the ONO film is partly silicided, the silicide layer is spaced more apart from the word gate, which can prevent short-circuiting. The silicide layer is configured not to be in direct contact with the ONO film by a presence of the non-silicide layers. Thus, the influences of the electric state of the silicide layer, and of the state of an oxide film on the silicide layer side of the ONO film can be reduced to a much smaller level. The nickel components of the silicide layer are prevented from being diffused into the ONO film, so that the charges stored in the nitride film can be prevented from being drawn into the nickel components. Such an arrangement can stabilize more the state of charges stored in the nitride film, make the charge distribution more uniform, and prevent the degradation in quality of the ONO film. As a result, the reliability and stability of the memory cell can be enhanced.
[0015]The invention can prevent short-circuiting between the word gate and the control gate. The instability of charges and nonuniformity of electrolytic distribution at the ONO film, the degradation in quality of the ONO film, and the like can be prevented, which can enhance the reliability and stability of the memory cell.

Problems solved by technology

However, the use of cobalt silicide or titanium silicide material makes it difficult to sufficiently decrease the resistance by the thinning effect of the silicide.
Thus, the miniaturization using these materials has become difficult.
When such a silicided part becomes thick, problems including an increase in leakage at the diffusion layer may be caused.
Thus, the electric state and the film thickness state can make the state of charges stored in the nitride film extremely unstable, and make the distribution of charges nonuniform.
In particular, nickel components of the nickel silicide may be partly diffused into the oxide film on the nickel silicide side to degrade the quality of the ONO film.
In that case, the charges stored in the nitride film can be prone to penetrate the nickel components.
In this way, such occurrence of unstable charges and nonuniform electrolytic distribution at the ONO film, and degradation in quality of the ONO film leads to a crash of data, which may significantly reduce reliability and stability of a memory cell.

Method used

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  • Nonvolatile semiconductor memory device and method of manufacturing nonvolatile semiconductor memory device
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  • Nonvolatile semiconductor memory device and method of manufacturing nonvolatile semiconductor memory device

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first exemplary embodiment

[0036]FIG. 2 is a cross-sectional view showing the structure of a nonvolatile semiconductor memory device according to a first exemplary embodiment of the invention. In the first exemplary embodiment, a flash memory cell having a TWIN-MONOS structure will be described as one example of a memory cell of the nonvolatile semiconductor memory device. The TWIN-MONOS structure is a structure having control gates formed at both sides of a word gate.

[0037]A memory cell 1 includes source / drain diffusion layers 32, a word gate insulating film 12, a word gate 22, control gates 24, ONO films (oxide nitride oxide films: oxide-nitride-oxide films) 14, sidewall insulating films 16, silicide layers 34 and 35, and LDD (lightly doped drain) diffusion layers 31.

[0038]The source / drain diffusion layers 32 are formed on both sides of the channel region over the surface of a semiconductor substrate 10. A dopant of the source / drain diffusion layer 32 may be, for example, arsenic (As), or phosphorus (P). Th...

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Abstract

A nonvolatile semiconductor memory device (and method of forming same) includes a word gate provided above a channel region of a semiconductor substrate via an insulating layer, a control gate provided at a side of the word gate, and a charge storage layer provided by an ONO film between the channel region and the control gate, and between the word gate and the control gate. The control gate includes a silicide layer including silicide containing nickel, and a non-silicide layer provided between the silicide layer and the charge storage layer.

Description

INCORPORATION BY REFERENCE[0001]This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2008-251758 which was filed on Sep. 29, 2008, the disclosure of which is incorporated herein in its entirety by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a nonvolatile semiconductor memory device, and to a method of manufacturing a nonvolatile semiconductor memory device.[0004]2. Description of Related Art[0005]A nonvolatile semiconductor memory device with a Metal-Oxide-Nitride-Oxide-Silicon (MONOS) structure is known. The nonvolatile semiconductor memory device includes a word gate provided above a channel region of a semiconductor substrate via an insulating layer, control gates provided at both sides of the word gate, and a charge storage layer provided both between the channel region and the control gate, and between the word gate and the control gate. An Oxide Nitride Oxide (ONO) ...

Claims

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Application Information

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IPC IPC(8): H01L29/792H01L21/28
CPCH01L21/28282H01L29/7923H01L29/42348H01L29/42344H01L29/40117
Inventor MATSUDA, TOMOKO
Owner RENESAS ELECTRONICS CORP
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