Multiple derating factor sets for delay calculation and library generation in multi-corner STA sign-off flow

Abstract

An apparatus and method to characterize a new process using an improved delay calculation. Multiple derating factors are used for different STA sign off corners that have a base corner with two pairs of off-corners. The approach of the present invention does not add any extra work in cell library characterization, while in the mean it increases the accuracy of the delay calculation and the library generation at corners other than standard corners.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001][none]BACKGROUND OF THE INVENTION[0002]1. Field of Invention[0003]The present invention relates generally to the art of microelectronic integrated circuits. In particular, the present invention relates to the art of computing delays for cells in ASICs.[0004]2. Description of Related Art[0005]An integrated circuit chip (hereafter referred to as an “integrated circuit” (IC), “ASIC”, or a “chip”) comprises cells and connections between the cells formed on a surface of a semiconductor substrate. The IC may include a large number of cells and require complex connections between the cells.[0006]A cell is a group of one or more circuit elements such as transistors, capacitors, and other basic circuit elements grouped to perform a function. Each of the cells of an IC may have one or more pins, each of which, in turn, may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surfa...

AI Technical Summary

Benefits of technology

[0030]Accordingly, an aspect of the present invention is a method to increase the accuracy when generating delay calculations when characterizing ASIC cells in low submicron processes.

[0032]Another aspect of the present invention is a method of increasing the accuracy of delay calculations and library generation at corners other than standard corners, such as off-corners.

[0033]Another aspect of the present invention is keep the library generation time to a minimum while maintaining acceptable accuracy.

[0034]Yet another aspect of the present invention is to propose a method for delay calculation flow to use multi-set of multi-point derating factors K, to do delay calculations or to generate off-corner libraries in STA timing sign off, all the while keeping the characterized base library calculation numbers to a minimum, speeding up the delay and characterization.

[0035]Thus the present invention enables a fast, accurate way for timing library generation for deep sub-micron semiconductors.

[0036]The sum total of all of the above advantages, as well as the numerous other advantages disclosed and inherent from the invention described herein, creates an improvement over prior techniques.

Problems solved by technology

Typically it is too time-consuming to build every cell in silicon and measure actual cell delays, instead, designers simulate the delay in a cell, a process called characterization.

Due to the large number of components and the exacting details required by the fabrication process, logical and physical design is not practical without the aid of computers.

Layout of the entire circuit cannot be handled due to the limitation of memory space as well as the computation power available.

However, more sign-off corners have a drawback: more library generation at each specific corner, which results in tremendous characterization time.

PVT is highly nonlinear, and this causes a decrease in accuracy when a corner library is far away from the base corner.

Images