Method of manufacturing semiconductor device

Abstract

Disclosed herein is a method for manufacturing a semiconductor device, the method including the steps of: forming a recess in an insulating film provided over a substrate; forming a plating seed layer in such a way that an inner wall of the recess is covered, the plating seed layer arising from sequential deposition of an alloy layer composed of copper and a metal other than copper and a conductive layer composed mainly of copper; burying a conductive layer composed mainly of copper by plating in the recess on which the plating seed layer is provided; and carrying out heat treatment to cause the metal in the alloy layer to react with a constituent in the insulating film, to thereby form a barrier film composed of a metal compound having a copper diffusion barrier function at an interface between the alloy layer and the insulating film.

Description

CROSS REFERENCES TO RELATED APPLICATIONS[0001]The present invention contains subject matter related to Japanese Patent Application JP 2006-222194 filed in the Japan Patent Office on Aug. 17, 2006, the entire contents of which being incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device that has a damascene structure in which a self-formed barrier film is provided between an interconnect or via and an interlayer insulating film.[0004]2. Description of the Related Art[0005]In a general process for forming a copper (Cu) interconnect in a semiconductor device, a damascene method is employed, in which an interconnect pattern is formed by filling an interconnect trench provided in an interlayer insulating film. In formation of a Cu interconnect by use of the damascene method, generally before bur...

AI Technical Summary

Benefits of technology

The present invention provides a method for manufacturing a semiconductor device that prevents separation of a conductive layer and enhances the uniformity of the coverage of the conductive layer across the substrate plane while suppressing interconnect resistance. The method involves sequentially carrying out the steps of forming a recess in an insulating film, depositing an alloy layer composed of copper and a metal other than copper and a conductive layer composed mainly of copper, plating the conductive layer in the recess, and carrying out heat treatment to cause the metal in the alloy layer to react with a constituent in the insulating film, thereby forming a barrier film composed of a metal compound having a copper diffusion barrier function at the interface between the alloy layer and the insulating film. This method reduces the burden on the plating step, enhances the adhesiveness between the conductive layer and the insulating film, and prevents the increase in resistance of the conductive layer due to elution of metal in the plating solution.

Problems solved by technology

However, the above-described manufacturing method involves the following problems.

This leads to the necessity for application of a large current in the plating step, and thus increases the burden on the plating step.

This causes unevenness of the plating growth of the conductive layer 18 across the plane of the substrate 11, which results in low uniformity of the coverage of the conductive layer 18.

Moreover, Mn on the surface side of the plating seed layer 17′ is easily eluted in a plating solution, which leads to a problem that the Mn eluted in the plating solution is buried in the interconnect trench 16 together with the conductive layer 18 and hence the interconnect resistance increases.

Images