Highly-scalable hardware-based traffic management within a network processor integrated circuit

Abstract

A technique for managing traffic within a network processor integrated circuit (IC) involves establishing multiple queue groups, associating a different hardware counter with each queue group, and then using the hardware counters to support rate shaping and scheduling of all of the queues in the queue groups. For example, 512 queue groups of thirty-two queues each queue group are established for a total of 16,384 (16 k) different queues and a different hardware counter is associated with each queue group for a total of 512 hardware counters. The group-specific hardware counters are used to implement hardware-based rate shaping and scheduling of all 16 k queues in a resource efficient manner that supports high throughput, e.g., on the order of 40 Gbps.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is entitled to the benefit of provisional U.S. Patent Application Ser. No. 60 / 856,525, filed Nov. 3, 2006, the disclosure of which is incorporated by reference herein in its entirety.FIELD OF THE INVENTION[0002]The invention relates generally to traffic management in packet and cell based network devices, and more particularly, to techniques for managing traffic within a network processor integrated circuit (IC).BACKGROUND OF THE INVENTION[0003]The Internet is fast becoming a medium that can provide voice, video, and data services to a large number of users, such as residential users. In order to provide Internet-based voice, video, and data services to a large number of users, the networking equipment at the edge of the network must be able to provide a high level of Quality of Services (QoS) control. QoS control, referred to generally as “traffic management,” involves controlling the rate at which bandwidth is consumed ...

AI Technical Summary

Benefits of technology

[0007]A technique for managing traffic within a network processor IC involves establishing multiple queue groups, associating a different hardware counter with each queue group, and then using the hardware counters to support rate shaping and scheduling of all of the queues in the queue groups. For example, 512 queue groups of thirty-two queues each queue group are established for a total of 16,384 (16 k) different queues and a different hardware counter is associated with each queue group for a total of 512 hardware counters. The group-specific hardware counters are used to implement hardware-based rate shaping and scheduling of all 16 k queues in a resource efficient manner that supports high throughput, e.g., on the order of 40 Gbps. Because multiple queues share the same hardware counter, a large number of queues can be rate shaped and scheduled using hardware-based techniques without using a separate hardware counter for each queue. Hardware counters take up a relatively large area on an IC device and therefore providing a separate hardware counter for each queue would require a large IC footprint or reduce the amount of area available on the IC for other circuitry. Even though multiple queues share the same hardware counter, queue-specific credit information is established so that each queue can be rate shaped to a queue-specific rate. Additionally, dividing the queues into queue groups enables scheduling to be accomplished in a hierarchical manner, thereby avoiding the need to arbitrate among the total set of queues (e.g., 16 k queues) in parallel.

Problems solved by technology

Hardware counters take up a relatively large area on an IC device and therefore providing a separate hardware counter for each queue would require a large IC footprint or reduce the amount of area available on the IC for other circuitry.

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