Semiconductor device and method of manufacturing the same

Abstract

On an SOI substrate, a hydrogen ion implantation section in which distribution of hydrogen ions peaks in a BOX layer (buried oxide film layer), and a single-crystal silicon thin-film transistor are formed. Then this SOI substrate is bonded with an insulating substrate. Subsequently, the SOI substrate is cleaved at the hydrogen ion implantation section by carrying out heat treatment, so that an unnecessary part of the SOI substrate is removed, Furthermore, the BOX layer remaining on the single-crystal silicon thin-film transistor is removed by etching. With this, it is possible to from a single-crystal silicon thin-film device on an insulating substrate, without using an adhesive. Moreover, it is possible to provide a semiconductor device which has no surface damage and includes a single-crystal silicon thin film which is thin and uniform in thickness.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a divisional of application Ser. No. 10 / 802,735, filed Mar. 18, 2004, which claims priority under 35 U.S.C. § 119(a) to Patent Application No. 2003-077283 filed in Japan on Mar. 20, 2003. The entire contents of Application No. 2003-077283 are hereby incorporated by reference.FIELD OF THE INVENTION [0002] The present invention relates to SOI technology, and particularly relates to a semiconductor device utilized for a high-performance integrated circuit formed on a low-priced general-purpose insulating substrate and a TFT-driven active matrix LCD, OLED and the like. BACKGROUND OF THE INVENTION [0003] There have been so-called active matrix driving devices which drive, for instance, liquid crystal display panels and organic EL display panels and are constructed in such a manner that a thin-film transistor (TFT) made of amorphous silicon (amorphous Si; a-Si) or polycrystalline silicon (p-Si) is formed on a glass substra...

AI Technical Summary

Benefits of technology

This approach allows for the creation of thin, uniform, and defect-free single-crystal silicon thin films on insulating substrates, enhancing transistor performance, reducing the short channel effect, and enabling the integration of high-performance devices without the need for adhesives, thus improving the manufacturing process and device characteristics.

Problems solved by technology

However, polycrystalline silicon has a localized state in the gap, which is caused due to reasons such as incomplete crystallinity and the defects around the crystal grain boundary, so that the mobility decreases and S-coefficient (subthreshold coefficient) increases.

For this reason, the performance of a transistor made of polycrystalline silicon is insufficient to form a high-performance device required for integrating systems such as a high-performance peripheral driver, memory, microprocessor, image processor, and timing controller.

However, according to the conventional semiconductor devices and manufacturing methods thereof, there is a problem in heat resistance because a high-performance device formed from a single-crystal silicon thin film is adhered with a glass substrate using an adhesive.

Due to this problem, there are limitations in the manufacturing process and device structure: For instance, it is impossible to form members such as a high-quality inorganic insulating film and TFT after carrying out adhering using an adhesive.

However, this method adopts, as a substrate, a crystallized glass including atoms of alkali, thereby being expensive and inferior in workability.

Furthermore, according to the method, the glass substrate has to be made from a 8-inch or 12-inch (Si) wafer, and hence it is not possible to adopt the method for a large-sized glass substrate (at least 300 mm×400 mm in size).

On this account, from a cost / size point of view, it is very difficult to adopt the method disclosed by the above-mentioned publication to display devices.

However, in the light of productivity, such active matrix substrates are still mainly made by forming a polycrystalline silicon on a large-sized glass substrate, so that the micro-fabrication necessary for obtaining high-performance and high-integration cannot sufficiently carried out.

This is because of the problems such as the following: In consideration of the swell, irregularity in thickness, expansion and contraction (especially contraction), and the size of an exposure region, it is difficult to increase the reduction ratio of reduced projection exposure.

Furthermore, the micro-fabrication is also limited by device characteristics, for instance, the fluctuation of the crystal grain boundary with respect to a transistor channel section is increased.

For the reasons above, it is extremely difficult to realize a device requiring high-performance and high-integration, such as an MPU, by adopting an arrangement of forming a polycrystalline silicon on a large-sized glass substrate.

That is to say, a layer damaged due to reasons such as dangling bond and crystal defect, the layer being harmful in terms of electric properties, has to be removed without causing the fluctuation in the transistor characteristics, which is caused due to irregular thickness of the silicon thin film.

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