MOS transistor

Abstract

A method of forming a MOS transistor, in which a co-implantation is performed to implant an implant into a source region and a drain region or a halo implanted region to effectively prevent dopants from over diffusion in the source region and the drain region or the halo implanted region, for obtaining a good junction profile and improving short channel effect. The implant comprises carbon, a hydrocarbon, or a derivative of the hydrocarbon, such as one selected from a group consisting of C, CxHy+, and (CxHy)n+, wherein x is a number of 1 to 10, y is a number of 4 to 20, and n is a number of 1 to 1000.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This is a divisional application of U.S. patent application Ser. No. 11 / 278,434 filed on Apr. 3, 2006, and the contents of which are included herein by reference.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates a method of forming a MOS transistor, and particularly a method of forming a MOS transistor having an improved short channel effect, comprising a step of co-implantation using an implant comprising carbon, hydrocarbon, or a derivative thereof. [0004] 2. Description of the Prior Art [0005] Field effect transistors (FETs) are important electronic devices in the fabrication of integrated circuits, and as the size of the semiconductor device becomes smaller and smaller, the fabrication of the transistors also improves and is constantly enhanced for fabricating transistors with smaller sizes and higher quality. [0006] In the conventional method of fabricating transistors, a gate structu...

AI Technical Summary

Benefits of technology

[0012] One object of the present invention is to provide a method of forming a MOS transistor with an improved short channel effect.

[0017] The method of forming a MOS transistor comprises a step of co-implantation to implant carbon, a hydrocarbon compound, or a derivative of the hydrocarbon compound, such as one selected from a group consisting of C, CxHy+, and (CxHy)n+, wherein x is a number of 1 to 10, y is a number of 4 to 20, and n is a number of 1 to 1000, within substantially the same place as that of the lightly doped drain or source, the source region and the drain region, or the halo implanted region. Therefore, after a rapid thermal process is performed, for example, by a conventional implanter and a spike annealing tool, the diffusion of dopants co-existing with the implants from the co-implantation can be reduced. That is, the diffusion of the dopants within the lightly doped drain or source, the source region and the drain region, or the halo implanted region can be effectively controlled, to obtain a good junction profile and an improved short channel effect.

Problems solved by technology

With the device scaling down, it's difficult to control the junction depth (Xj) and also reduce the access resistance.

But from 65 nm node and beyond, the conventional As implantation and spike RTP can hardly meet the nFET SCE requirement.

Unfortunately the advanced activation tools (for example, flash or laser anneal) are under development and not mature.

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