Methods for manufacturing silicon wafer and silicon epitaxial wafer, and silicon epitaxial wafer

Abstract

There is provided a method for manufacturing a silicon wafer or a silicon epitaxial wafer capable of imparting an excellent IG capability thereto in a stable manner by simultaneously realizing higher density of oxide precipitates and larger sizes thereof at a stage prior to a device fabrication process. The present invention is a method for manufacturing a silicon wafer wherein the silicon wafer is subjected to heat treatment to impart a gettering capability thereto comprising at least the following three steps of: a temperature raising step A for generating oxygen precipitation nuclei; a temperature raising step B for growing the oxygen precipitation nuclei; and a constant temperature keeping step C for growing the oxygen precipitation nuclei into oxide precipitates of larger sizes.

Description

TECHNICAL FIELD [0001] The present invention relates to methods for manufacturing a silicon wafer and a silicon epitaxial wafer capable of obtaining the silicon wafer and the silicon epitaxial wafer having a defect-free layer (a DZ layer or an epitaxial layer) in the vicinity of a surface thereof and oxide precipitates high in gettering capability in the bulk thereof through heat treatment with extreme efficiency and simplicity, and a silicon epitaxial wafer. BACKGROUND ART [0002] Most of silicon wafers used widely as substrates of semiconductor devices are manufactured from a silicon single crystal grown in a Czochralski (CZ) method. The silicon single crystal grown in the CZ method contains interstitial oxygen as impurities at concentration of about 1018 atoms / cm3. The interstitial oxygen turns into a supersatulated state in a thermal history from solidification of a melt till cooling down thereof to room temperature during a crystal growth step (hereinafter which may be referred ...

AI Technical Summary

Benefits of technology

"The present invention provides a method for manufacturing a silicon wafer or a silicon epitaxial wafer that can efficiently form a DZ-IG structure with excellent IG capability in a stable manner. The method involves a temperature raising step A for generating oxygen precipitation nuclei, a temperature raising step B for growing the oxygen precipitation nuclei, and a constant temperature keeping step C for growing the oxygen precipitation nuclei into oxide precipitates of larger sizes. By simultaneously realizing higher density of oxide precipitates and larger sizes of grown-in precipitation nuclei, the method can efficiently form a DZ-IG structure with excellent IG capability in a device fabrication process. The method can also efficiently grow grown-in precipitation nuclei generated in a crystal thermal history in a short time with annihilation being suppressed to the lowest level possible. The method can be used to manufacture silicon wafers with stable IG capability and high efficiency in a lower temperature heat treatment process."

Problems solved by technology

A usual as-grown wafer (a wafer subjected to no heat treatment except for general oxygen donor anihilation heat treatment) has no IG capability because oxygen precipitation nuclei existing at a stage prior to a device fabrication process are extremely small.

Since density of oxygen precipitation nuclei generated during a crystal thermal history depends on the length of the thermal history, there arises a problem that the density is largely fluctuated according to crystal pulling conditions such as a pulling rate or a position in the direction of a crystal growth axis.

On the other hand, when oxide precipitates exist in a device fabrication region in the vicinity of a wafer surface, degradation of the device characteristics occurs.

However, this treatment is long in the total process for heat treatment, resulting in poor efficiency.

When the COPs and voids are present in the device fabrication region, degradation of the device characteristics occurs too.

However, in this case, a problem arises that thermal stress causes slip generation.

However, even when a wafer added with nitrogen is used, there is no change in that it is necessarily subjected to high-temperature heat treatment at about 1200° C. As the wafer diameter becomes larger, the slip more easily generates; therefore especially in a 300 mm wafer that is the mainstream hereafter, there becomes a great problem need of high-temperature heat treatment at about 1200° C. or higher.

Further, since the area where void defects are annihilated is in a very thin surface layer of the order of several μm from the surface, the void defects may degrade device characteristics in a device using a surface layer deeper than the very thin surface layer as a device fabrication region.

Accordingly, in an epi wafer, there arises a problem that an IG capability deteriorates.

Furthermore, the lower the heat treatment temperature is, the smaller the critical size becomes.

However, if the heat treatment temperature is lowered, a growth rate of precipitation nuclei is slowed, so a long time of heat treatment is required for growing the precipitation nuclei to sizes not to be annihilated even in an epi step, which is not preferable because of reduction in productivity.

Furthermore, if there exist oxide precipitates having sizes not to be annihilated even in an epi step, in a recent device fabrication process having a lower temperature and a shorter time, no further growth of the oxide precipitates can be expected in heat treatment of the device fabrication process.

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