Method and apparatus for reducing charge density on a dielectric coated substrate after exposure to large area electron beam

Abstract

Embodiments in accordance with the present invention relate to a number of techniques, which may be applied alone or in combination, to reduce charge damage of substrates exposed to electron beam radiation. In one embodiment, charge damage is reduced by establishing a robust electrical connection between the exposed substrate and ground. In another embodiment, charge damage is reduced by modifying the sequence of steps for activating and deactivating the electron beam source to reduce the accumulation of charge on the substrate. In still another embodiment, a plasma is struck in the chamber containing the e-beam treated substrate, thereby removing accumulated charge from the substrate. In a further embodiment of the present invention, the voltage of the anode of the e-beam source is reduced in magnitude to account for differences in electron conversion efficiency exhibited by different cathode materials.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS [0001] This application is a non-provisional application of and claims the benefit of U.S. Provisional Application No. 60 / 558,009, filed on Mar. 30, 2004, which is herein incorporated by reference in its entirety for all purposes.BACKGROUND OF THE INVENTION [0002] Semiconductor device geometries have dramatically decreased in size since integrated circuits were first introduced several decades ago, and all indications are that this trend will continue on. Today's wafer fabrication plants are routinely producing devices having 0.25 μm and even 0.18 μm feature sizes, and the plants of the future will soon be producing devices having even smaller geometries. [0003] As device sizes become smaller and integration density increases, one issue that has become an increasing concern to semiconductor manufacturers is that of inter-level “crosstalk.” Crosstalk is the undesired coupling of an electrical signal on one metal layer onto another metal layer,...

AI Technical Summary

Benefits of technology

[0010] Embodiments in accordance with the present invention relate to a number of techniques, which may be applied alone or in combination, to reduce charge damage of substrates exposed to electron beam radiation. In accordance with one embodiment, charge damage may be reduced by establishing a robust electrical connection between the exposed substrate and ground. In accordance with another embodiment, charge damage may be reduced by modifying the sequence of steps for activating and deactivating the electron beam source, thereby reducing charge accumulation on the substrate. In accordance with still another embodiment, a plasma may intentionally be struck in the chamber following e-beam exposure, thereby removing accumulated charge from the substrate. In accordance with still a further embodiment of the present invention, voltage on the anode of the e-beam source may be reduced in magnitude to account for differences in the electron conversion efficiency of different anode materials.

Problems solved by technology

As device sizes become smaller and integration density increases, one issue that has become an increasing concern to semiconductor manufacturers is that of inter-level “crosstalk.” Crosstalk is the undesired coupling of an electrical signal on one metal layer onto another metal layer, and arises when two or more layers of metal with intervening insulating or dielectric layers are formed on a substrate.

Undesired coupling of electrical signals can also occur between adjacent conductive traces, or lines, within a conductive layer.

Another issue that is becoming more of a concern with decreasing feature sizes is the “RC time constant” of a particular trace.

Thus high RC time constants can slow down the operation of a circuit.

Unfortunately, shrinking circuit geometries produce narrower traces, which results in higher resistivity.

Excessive charge buildup may result in unwanted electrical effects, including electrical breakdown across fragile structures such as MOS gate oxides, resulting in possible damage to the semiconductor devices.

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